tda19978bhv NXP Semiconductors, tda19978bhv Datasheet - Page 11

• Manufacturer Part Number: tda19978bhv
• Description: Quad Hdmi 1.3a Receiver Interface With Equalizer Hdtv Up To 1080p, Up To Uxga For Pc Formats
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA19978B_1
Product data sheet
8.10 Audio PLL
8.11 Audio formatter
The TDA19978B includes a two-channel status decoder supporting multi-channel
reception for audio sample packets. This enables the user to obtain channel status
information from the IEC 60958/IEC 61937 stream such as:
Refer to IEC 60958/IEC 61937 specifications for more details.
An update of each InfoFrame or the channel status content is indicated by a register bit
and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.
The TDA19978B generates a 128/256/512
audio DACs without an integrated PLL, such as the UDA1334BTS. The programming of
the audio PLL can be either automatic, using the audio clock regeneration parameters
found in the Data Islands or set manually using the I
All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz,
96 kHz and 192 kHz are accepted by the device.
Audio samples can be output in either S/PDIF, I
or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins
(AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using
these pins. The audio port mapping depends on the channel allocation (see
Table 5
•
•
•
The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958)
Copyright protection
Sampling frequency
and
Table 6
for detailed information).
Rev. 01 — 7 August 2008
Quad HDMI 1.3a receiver with digital processing
f
s
2
system clock enabling the use of simple
S-bus formats or DSD (SACD). In I
2
C-bus.
TDA19978B
© NXP B.V. 2008. All rights reserved.
Table
2
4,
11 of 36
S-bus