adm8515 Infineon Technologies Corporation, adm8515 Datasheet
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The information in this document is subject to change without notice. Edition 2005-11-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe ...
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... Revision History: 2005-11-08, Rev. 1.21 Previous Version: Page/Date Subjects (major changes since last revision) 2003-04-10 Rev. 1.0: First release of ADM8515/X 2003-08-28 Rev. 1.1: Updated pin 5 and 6 definition 2004-05-07 Rev. 1.2: Updated to include Infineon-ADMtek 2005-09-13 Rev. 1.21: when changed to the new Infineon format 2005-11-01 Minor change. Included Green package information Trademarks ® ...
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... Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 USB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1 Get Register (Vendor Specific) Single/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2 Set Register (Vendor Specific) Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 Get Status (Device 5.4 Get Status (Interface 5.5 Get Status (EP1) Bulk 5.6 Get Status (EP2) Bulk OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.7 Get Status (EP3) Interrupt Data Sheet 4 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.1 USB Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.2 EEPROM Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.3 GPIO Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.2 EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.3 MII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.1 Appendix 1 EEPROM CONTENT & Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data Sheet 5 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Packet Form when Transmit Figure 6 EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 7 Transmit Signal Timing Relationships at the MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 8 Received Signal Timing Relations at the MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 9 MDIO Sourced by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 10 MDIO Sourced by PHY Figure 11 P-LQFP-100-1 (Plastic Low Profile Quad Flat Package Data Sheet 6 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Table 44 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 45 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 46 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 47 Data Stage: wLength Field Specifies the Total byte Count to Return . . . . . . . . . . . . . . . . . . . . . . 71 Table 48 *8/64 := USB 1.1/2 Table 49 *8/64 := USB 1.1/2 Table 50 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 51 Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 52 Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 53 Interface 0 Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Data Sheet 7 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 83 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 84 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 85 Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 86 USB Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 87 EEPROM Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 88 GPIO Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 89 EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 90 Dimensions for 100 Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 91 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Data Sheet 8 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... USB interface is 480 Mbit/s belonging to a high speed USB device. The ADM8515/X supports all USB commands, 4 endpoints and suspend/resume function. The ADM8515/X’s LAN PHY supports 100 Base TX (100 Mbit/s mode) and 10 Base T (10 Mbit/s mode) full-duplex operations. It uses the auto-negotiation function to optimize the network traffic and the built-in 24K bytes SRAM for receiving buffer, especially for 100 Mbit/s ...
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... Windows 98/ME/2000/XP driver – Linux driver – WinCE 3.0 & 4.0 drivers – EEPROM burn-in program – MFG testing program • Miscellaneous – Supports 6 GPIO pins – Provides 100-pin LQFP package – 3.3 V power supply with 5 V/3.3 V I/O tolerance Data Sheet 10 ADM8515/X Product Overview Rev. 1.21, 2005-11-08 ...
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... Block Diagram Figure 1 Block Diagram 1.4 Conventions 1.4.1 Data Lengths qword 64 bits dword 32 bits word 16 bits byte 8 bits nibble 4 bits Data Sheet 11 ADM8515/X Product Overview Rev. 1.21, 2005-11-08 ...
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... Interface Description 2.1 Pin Diagram Pin Diagram of ADM8515/X. Figure 2 Pin Diagram Data Sheet 12 ADM8515/X Interface Description Rev. 1.21, 2005-11-08 ...
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... Pin Description by Function ADM8515/X pins are categorized into one of the following groups: • Host Interface • MII Interface • Physical Layer Interface • LED Display Mode • EEPROM Interface • Regulator Pins • Power Pins • Miscellaneous Table 2 Abbreviations for Pin Type ...
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... Pull Down with 510 Ohm Precise Resistor ( ± 1%) Pull up with a 1.5 k Ohm Resistor O USB Line State They directly reflect the current state of the DP (LINE1) and DM (LINE0) signals, see ADM8515/X Interface Description Table 5 Description 0: SE0 1: “J” State 2: “K” State 3: SE1 Rev. 1.21, 2005-11-08 ...
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... MII Interface Note: Program ADM8515/X as MAC-only mode, set register 81 Table 6 MII Interface Pin or Ball Name No. 53 COL 52 CRS 72 MDC 73 MDIO 64 RXCLK 71 RXD3 69 RXD2 68 RXD1 67 RXD0 65 RXDV 63 RXER 62 TXCLK Data Sheet [4:2] = 001 H Pin Buffer Function Type Type I Collision Detected This signal is asserted high asynchronously by the external physical unit upon detection of a collision on the medium ...
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... Magnetic. O Transmits Outputs The differential transmits outputs of 100BASE-TX or 10BASE-T, these pins directly output to Magnetic. I Reference Bias Resistor To be tied to an external 10.0 kΩ (1%) resistor which should be connected to the analog ground at the other end. O PHY Test Pins 16 ADM8515/X Interface Description Rev. 1.21, 2005-11-08 ...
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... EEPROM 0B[7: LED0: Link 10 (LED on when link on 10Mbit/s) and Activity (Flash with 10Hz when ADM8515/X is receiving or transmitting without collision)LED1: Link 100 (LED on when link on 100Mbit/s) and Activity (Flash with 10Hz when ADM8515/X is receiving or transmitting without collision) LED2: Full duplex (keeps on when in full duplex ...
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... VSA 99 VCTRL 97 VSENSE Note: ADM8515 dual power device, it needs both 3.3 V and 2.5 V power supply. Inside the chip, there is an embedded 3 2.5 V power regulator that can generate the needed 2.5 V power to supply the chip. The reference schematics design is shown in Data Sheet Pin Buffer ...
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... P 2.5 V Digital Power Supply P Digital Ground P 3.3 V Analog Power Supply P Analog Ground P 3.3 V Power Supply for Transmitter P Ground for VAAT P 3.3 V Power Supply for Receiver P Ground for VAAR P 3.3 V Power Supply for PHY P Ground for VAAREF 19 ADM8515/X Interface Description Rev. 1.21, 2005-11-08 ...
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... GPIO0 92, 91 TEST 1 9, 10, 11, 14, TEST2 15, 16, 17, 18 Data Sheet Pin Buffer Function Type Type I/O General Purpose Input/Output Pins These pins are used as general purpose Input/Output pins. These pins are internal pull-low. I Test Pins I/O Test Pins 20 ADM8515/X Interface Description Rev. 1.21, 2005-11-08 ...
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... After TX_EN goes low for more than 500 ms, the TP transmitter will reactivate and COL gets de-asserted. Setting Jabber Disable will disable the jabber function. When the SQE test is enabled, a COL pulse is asserted after each transmitted packet. SQE is enabled in 10Base-T by default. Data Sheet 21 ADM8515/X Function Description Rev. 1.21, 2005-11-08 ...
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... NAK if accessing to bulk OUT endpoint is invoked. Thus additional USB packet won’t be written into TX FIFO until TX FIFO has free space. 3.4 TX FIFO and RX FIFO RX FIFO is a one-port 512 byte FIFO and TX FIFO is a two-port 2 Kbyte FIFO Data Sheet 22 ADM8515/X Function Description Rev. 1.21, 2005-11-08 ...
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... Indicates received multicast frame. long_pkt Indicates received packet length > 1518 bytes. runt_pkt Indicates received packet length < 64 bytes. crc_err Indicates CRC check error. dribble_bit Indicates packet length is not integer multiple of 8- bit. reserved reserved 23 ADM8515/X Function Description Rev. 1.21, 2005-11-08 ...
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... Interrupt Packet Form Offset5 wakeup_status(Reg7A ) H Data Sheet 2nd Byte in 1st USB Packet {reserved[4:0], len[10:8]} Offset2 Offset3 ) rx_status(Reg2D ) rx_lostpkt(Reg2E H H Offset6(1B) Packet number in RX FIFO (Reg82 ) H 24 ADM8515/X Function Description The Following Packets Ethernet packet Offset4 ) rx_lostpkt(Reg2F H Offset7(1B) 7’b00, length error Rev. 1.21, 2005-11- ...
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... Reserved 7 RPNBFC Receive Packet Number Based Flow Control ORFBFC Occupied Receive FIFO Based Flow Control EP1C EP1 Control Res8 Reserved 8 Data Sheet End Address 0000 0082 ADM8515/X Registers DescriptionSystem Registers Note Offset Address Page Number ...
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... ... ADM8515/X Page Number ...
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... Register is readable and writable by SW Value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= Target for development.) SW can only read this register SW can only read this register 27 ADM8515/X Page Number ...
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... SW can read and write this register Register is readable and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is readable and writable by SW. Description Offset ADM8515/X Reset Value 09 H Rev. 1.21, 2005-11-08 ...
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... ICRC, Includes CRC in receive packet B Offset 01 H Description Full Dublex 0 HDM, Half-duplex mode B 1 FDM, Full-duplex mode B 10mode 0 10Base, 10Base-T mode B 1 100Base, 100Base-T mode B Reset MAC After write 1, HW will clear this bit after MAC reset. 29 ADM8515/X Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... FABP, Filter all bad packet B 1 RBPP, Receives bad packets which pass the address filter B EP3 Read Cleared 0 AEP3, Access EP3, no effect to those registers OEP3, Once EP3 is accessed, those registers (2B-2F, 7A) will be B cleared. 30 ADM8515/X Reset Value 40 H (Receive packet H Rev. 1.21, 2005-11-08 ...
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... Res18 Reserved 18 Res19 Reserved 19 Res 20 Reserved 20 Res 21 Reserved 21 Res 22 Reserved 22 Res 23 Reserved 23 Res 24 Reserved 24 Res 25 Reserved 25 Data Sheet Registers DescriptionSystem Registers Offset 03 H Description Reserved 31 ADM8515/X Reset Value 00 Offset Address Page Number ...
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... Multicast Address 1 Field Bits Type MAB1 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 08 H Description Multicast 0 Multicast address byte [7:0] Offset 09 H Description Multicast 1 Multicast address byte [15:8] 32 ADM8515/X Offset Address Page Number ... Reset Value 00 Reset Value 00 Rev. 1.21, 2005-11- ...
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... Field Bits Type MAB2 7:0 rw Multicast Address 3 MA3 Multicast Address 3 Field Bits Type MAB3 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 0A H Description Multicast 2 Multicast address byte [23:16] Offset 0B H Description Multicast 3 Multicast address byte [31:24] 33 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Field Bits Type MAB4 7:0 rw Multicast Address 5 MA5 Multicast Address 5 Field Bits Type MAB5 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 0C H Description Multicast 4 Multicast address byte [39:32] Offset 0D H Description Multicast 5 Multicast address byte [47:40] 34 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Field Bits Type MAB6 7:0 rw Multicast Address 7 MA7 Multicast Address 7 Field Bits Type MAB7 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 0E H Description Multicast 6 Multicast address byte [55:48] Offset 0F H Description Multicast 7 Multicast address byte [63:56] 35 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... EID1 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 10 H Description Ethernet ID 0 The 1st byte of Ethernet ID is automatically loaded from EEPROM after HW reset. Offset 11 H Description Ethernet ID 1 The 2nd byte of Ethernet ID. 36 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Ethernet ID 3 EID3 Ethernet ID 3 Field Bits Type EID3 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 12 H Description Ethernet ID 2 The 3rd byte of Ethernet ID. Offset 13 H Description Ethernet ID 3 The 4th byte of Ethernet ID. 37 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Ethernet ID 5 EID5 Ethernet ID 5 Field Bits Type EID5 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 14 H Description Ethernet ID 4 The 5th byte of Ethernet ID. Offset 15 H Description Ethernet ID 5 The 6th byte of Ethernet ID. 38 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... This field specifies the threshold for transmitting the PAUSE frame. As the received packet number is more than or equal to this field, the PAUSE frame is sent automatically by HW. Flow Control Packet 1 RPN, Enable pause frame transmission bases on receive packet B number 39 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... EEP1, Enable EP1 send 1-byte 00 when more than frame_ B interval’s NAK is received Internal Test Mode A This value is used for internal test mode. Internal Test Mode B This value is used for internal test mode. 40 ADM8515/X Reset Value 00 H Reset Value 04 H Rev. 1.21, 2005-11-08 ...
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... This bit enable the BIST function and also drives the “ reset” signal in BIST module. 0 EBI, Enable BIST function B 1 DBI, Disable BIST function B Offset 20 H Description ROM Offset SW sets this register when access to EEPROM. Offset ADM8515/X Reset Value 05 H Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... EEPROM Read: The data red from EEPROM will be stored in this register Offset 22 H Description ROM Data High EEPROM Write: The data set in this register will be written to EEPROM EEPROM Read: The data red from EEPROM will be stored in this register 42 ADM8515/X Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Set initiate a read access to EEPROM. SW sets this bit after it well setting the rom_offset. Write Access to EEPROM wr_eeprom Set initiate a write access to EEPROM. SW set this bit after it well setting the rom_offset, romdata_lo and romdata_hi. Offset 25 H Description MII PHY Address 43 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... SW set this register when write to PHY register. HW set this register when read data from PHY register. Offset 27 H Description PHY Data High SW set this register when write to PHY register. HW set this register when read data from PHY register. 44 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Description USB Bus in Resume State It is cleared by reading this register. 1 RS, Means USB bus in resume state B USB Bus in Suspend State It is cleared by reading this register. 1 SS, Means USB bus in suspend state B 45 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... It is cleared by reading this register or after EP3 is accessed 1 NC, Means no carrier B Carrier Loss It is cleared by reading this register or after EP3 is accessed 1 CL, Means carrier loss B Jabber Time Out It is cleared by reading this register or after EP3 is accessed 1 JTO, Means jabber time out B 46 ADM8515/X Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... H Description RX Pause It is cleared by reading this register or after EP3 is accessed 1 PF, Means a PAUSE frame is received B RX Overflow It is cleared by reading this register or after EP3 is accessed 1 RO, Means received SRAM overflow B 47 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... EP3 is accessed. Offset 2F H Description RX Lost Packet Counts The [7:0] of lost packet counts due to receive FIFO overflow cleared by reading this register or after EP3 is accessed Offset ADM8515/X Reset Value 00 H Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Wakeup Frame 0 Offset WUF0O_0 Wakeup Frame 0 Offset Field Bits Type F0O 7:0 rw Data Sheet Registers DescriptionSystem Registers Description The 128 Mask Bits for Frame 0 Offset 40 H Description Offset for Wakeup Frame 0 49 ADM8515/X Offset Address Page Number 31 H ... Reset Value 00 Rev. 1.21, 2005-11-08 H ...
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... Wakeup Frame 0 CRC High Field Bits Type F0CRCH 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 41 H Description The Low Byte of CRC16 Match for Frame 0 Offset 42 H Description The High Byte of CRC16 Match for Frame 0 50 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Wakeup Frame 1 Offset Field Bits Type F1O 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 48 H Description The 128 Mask Bits for Frame 1 Offset 58 H Description Offset for Wakeup Frame 1 51 ADM8515/X Reset Value 00 Offset Address Page Number 49 H ... Reset Value 00 Rev. 1.21, 2005-11- ...
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... Wakeup Frame 1 CRC High Field Bits Type F1CRCH 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 59 H Description The Low Byte of CRC16 Match for Frame 1 Offset 5A H Description The High Byte of CRC16 Match for Frame 1 52 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Wakeup Frame 2 Offset Field Bits Type F2O 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 60 H Description The 128 Mask Bits for Frame 2 Offset 70 H Description Offset for Wakeup Frame 2 53 ADM8515/X Reset Value 00 Offset Address Page Number 61 H ... Reset Value 00 Rev. 1.21, 2005-11- ...
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... Wakeup Frame 2 CRC High Field Bits Type F2CRCH 7:0 rw Data Sheet Registers DescriptionSystem Registers Offset 71 H Description The Low Byte of CRC16 Match for Frame 2 Offset 72 H Description The High Byte of CRC16 Match for Frame 2 54 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Enable Wakeup Frame 1 1 EWF1, Enables wakeup frame1 wakeup function B Enable Wakeup Frame 2 1 EWF2, Enables wakeup frame2 wakeup function B CRC-16 Initial Type 0 CRC16, CRC-16 initial contents = 0000 B 1 CRC16, CRC-16 initial contents = ffff B 55 ADM8515/X Reset Value Rev. 1.21, 2005-11-08 ...
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... It is cleared by reading this register. 1 RMP, means ADM8515/X receives a magic packet B Receives a Link Status Change It is cleared by reading this register. 1 RLS, means ADM8515/X receives a link status change B Receives a Wakeup Frame It is cleared by reading this register. 1 RWF, Means ADM8515/X receives a wakeup frame B ...
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... B 1 OUT, GPIO4 is used for output B GPIO4 Output Value When GPIO4 is used for output, this value is driven to GPIO4 pin. GPIO4 Input Value When GPIO4 is used for input, this field reflects the status of GPIO4. Default is pulled-down. 57 ADM8515/X Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... IN, GPIO0 is used for input B 1 OUT, GPIO0 is used for output B GPIO0 Output Value When GPIO0 is used for output, this value is driven to GPIO0 pin. GPIO0 Input Value When GPIO0 is used for input, this field reflects the status of GPIO0. 58 ADM8515/X Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... IN, GPIO2 is used for input B 1 OUT, GPIO2 is used for output B GPIO2 Output Value When GPIO2 is used for output, this value is driven to GPIO2 pin. GPIO2 Input Value When GPIO2 is used for input, this field reflects the status of GPIO2. 59 ADM8515/X Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... This value could be updated from EEPROM offset 0A[4:2]. 000 TS, Tri-state MII pins B 001 EM, enables MAC’s MII signals to external MII pins B 010 EPHY, enables PHY’s MII signals to external MII pins B 011 MM, Monitor mode MII B 60 ADM8515/X Reset Value 00 H Reset Value 00 H Rev. 1.21, 2005-11-08 ...
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... Data Sheet Offset 82 H Description Packet Number Received packet number from last access this register. This register is controlled by Reg 02[6] to decide read clear or not. End Address 0000 0006 ADM8515/X Registers DescriptionPHY Registers Reset Value Note Offset Address Page Number ...
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... Power Down 0 NO, Normal operation B 1 PD, Power Down B Isolate 0 NO, normal operation B 1 IPHY, isolate PHY from MII B Restart Autonegotiation 1 RAN, Restarts Auto-neg B Duplex Mode 0 HA, Half B 1 FU, Full B Collision Test Not implemented 62 ADM8515/X Registers DescriptionPHY Registers Reset Value Rev. 1.21, 2005-11-08 1000 H ...
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... PHY is 100BASE-X half duplex capable B 10Base-T Full Duplex 0 , PHY is not 10Mbit/s Full duplex capable PHY is 10Mbit/s Full duplex capable B 10Base-T Half Duplex 0 , PHY is not 10Mbit/s Half duplex capable PHY is 10Mbit/s Half duplex capable B 63 ADM8515/X Registers DescriptionPHY Registers Reset Value Rev. 1.21, 2005-11-08 7849 H ...
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... PHY can Auto-Negotiate B Link Status 0 , Link is down Link Jabber Detect Only used in 10Base-T mode. Reads 100Base-TX mode 1 , Jabber condition detect B Extended Capability 0 , Basic register set capabilities only Extended register capable ADM8515/X Registers DescriptionPHY Registers Rev. 1.21, 2005-11-08 ...
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... PHY Identifier[31-16] OUI (bits 3-18) Offset 3 H Description PHY Identifier[15-10] OUI (bits 19-24) PHY Identifier[9-4] Manufacturer’s Model Number (bits 5-0) PHY Identifier[3-0] Revision Number (bits 3-0);Register 3, bit bit of PHY Identifier 65 ADM8515/X Registers DescriptionPHY Registers Reset Value 001D Reset Value Rev. 1.21, 2005-11-08 H 2411 H ...
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... Half Duplex Technology ability bit A0 0 10NHD, Unit is not capable of Half Duplex 10BASE 10HD, Unit is capable of Half Duplex 10BASE-T B Selector Field Identifies type of message being sent. Currently only one value is defined. 66 ADM8515/X Registers DescriptionPHY Registers Reset Value Rev. 1.21, 2005-11-08 0001 H ...
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... Technology Ability Link Partner technology ability field. Selector Field Link Partner selector field Offset 6 H Description Parallel Detection Fault 0 NFD, No fault detected B 1 FD, Local Device Parallel Detection Fault B 67 ADM8515/X Registers DescriptionPHY Registers Reset Value Reset Value Rev. 1.21, 2005-11-08 0000 H 0004 H ...
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... PR, A New Page has been received B Link Partner Auto Negotiation Able 0 NAN, Link Partner is not Auto negotiation able B 1 AN, Link Partner is Auto negotiation able B wValue(2B) wIndex(2B) 0 {RegIndex[0:7], 00} Offset1(1B) {RegIndex+1) wValue(2B) wIndex(2B) 0 {RegIndex[0:7], 00} Offset2(1B) {RegIndex+2} 68 ADM8515/X wLength(2B) length Offset2(1B) {RegIndex+2) wLength(2B) Length Offset3(1B) {RegIndex+3} Rev. 1.21, 2005-11-08 ...
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... H D wValue(2B) wIndex(2B) 0000 0700 Offset1(1B) 12 wValue(2B) wIndex(2B D[1]: Remote Wakeup Register of remote_wakeup wValue(2B) wIndex(2B ADM8515/X USB CommandGet Status (Device) wLength(2B) 0100 D wLength(2B) 1400 Offset2(1B) 13 wLength L(1B) wLength H(1B D[0]:Self Powered 1 wLength L(1B) wLength H(1B ...
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... D[15:1] 0 Data Sheet wValue(2B) wIndex L(1B) wIndex H(1B) wLength 0 81 D[0]: Halt Register of ep1_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength 0 02 D[0]: Halt register of ep2_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength 0 83 D[0]: Halt register of ep3_halt 70 USB CommandGet Status (EP1) Bulk IN L(1B L(1B L(1B Rev. 1.21, 2005-11-08 ADM8515/X wLength H(1B) 0 WLength H(1B) 0 wLength H(1B) 0 ...
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... Offset 5 (Sub Offset 6 Class Code) (Protocol) FF Offset 11 Offset 12 (releaseID (productID) High Low 01 Offset 14 (m Offset 15 (Product) anufacture) 01 wLength L(1B) 0 Length low Offset 3 Offset 4 (TotalLength) High (NumInterface) 00 Rev. 1.21, 2005-11-08 ADM8515/X wLength H(1B) Length high Offset 7 (EP0 MaxPktSize) 8/64 wLength H(1B) Length high ...
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... Offset 4 Offset 6 (MaxPktSize) (Interval) High / 00H/02H Offset 5 Offset 6 (MaxPktSize) (Interval) High ) 00(1 ) ep3_interval wLength Low(1B) 0000 Length Low Offset3 (LanguageID Rev. 1.21, 2005-11-08 ADM8515/X 00 Offset 8 (StringInd ex) 00 wLength High(1B) Length High ...
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... Low(1B) 0904 Length Low String wLength Low(1B) 0904 Length Low String wLength Low(1B) 0904 Length Low String wLength wLength Low(1B) High(1B Rev. 1.21, 2005-11-08 ADM8515/X wLength High(1B) Length High wLength High(1B) Length High wLength High(1B) Length High ...
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... L(1B) wValue H(1B) wIndex(2B USB CommandGet Interface wLength wLength Low(1B) High(1B wLength L(1B) 0 Length low Offset 4 (class) Offset 5 (subclass Offset 8 (No of other speed configuration wLength L(1B) 0 Length low Rev. 1.21, 2005-11-08 ADM8515/X wLength H(1B) Length high ) wLength H(1B) Length high ...
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... H Offset 6( Offset 7 IntfSubCl (IntfProto ass) col) ) FF Offset 5( Offset 6 MaxPktSize) (Interval) High ( 00 Offset 4 Offset 6 (MaxPktSize) (Interval) High ( 00 Offset 5 Offset 6 (MaxPktSize) (Interval) High ) 00(1 ) ep3_interval wIndex(2B) wLength(2B Rev. 1.21, 2005-11-08 ADM8515 Offset 8 (StringInd ex) 00 ...
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... Data Sheet USB CommandSet Feature (Device) Remote Wakeup wValue L(1B) WValue H(1B wValue(2B) WIndex L(1B) 0000 EP no wValue(2B) WIndex H(1B) 0000 EP no wValue(2B) WIndex H(1B) 0002 Test selector 76 ADM8515/X wIndex(2B) wLength(2B wIndex L(2B) WLength(2B wIndex H(2B) WLength(2B wIndex H(2B) WLength(2B Rev. 1.21, 2005-11-08 ...
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... Min. Typ. 3.0 – 4.4 – DD Symbol Values Min. Typ. V 2.0 – – – 0.2 – 0.8 – ADM8515/X Electrical Characteristics Unit Note / Test Condition Max. 3.6 V – V +0.5 V – +0.5 V – DD °C 150 – – 2000 V – Unit Note / Test Condition Max ...
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... Timing 6.4.1 Reset Timing ADM8515/X can be reset either by hardware, software or USB reset. • A hardware reset is accomplished by asserting the RST# pin after powering up the device. It should have a duration of at least 100 ms to ensure the external 12 MHz crystal is in stable and correct frequency. All registers will be reset to default values. • ...
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... When ADM8515/X sees an SE0 on USB bus for more than 2.5 s. This USB reset will reset all registers to default values. 6.4.2 EEPROM Interface Timing Table 89 EEPROM Interface Timing Parameter EESK Clock Frequency EECS Setup Time to EESK EECS Hold Time from EESK EEDO Hold Time from EESK EEDO Output Delay to “ ...
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... MII Interface Timing Figure 7 Transmit Signal Timing Relationships at the MII Figure 8 Received Signal Timing Relations at the MII Data Sheet Electrical Characteristics 80 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Figure 9 MDIO Sourced by STA Figure 10 MDIO Sourced by PHY Data Sheet Electrical Characteristics 81 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Packaging Package Outline of ADM8515/X Figure 11 P-LQFP-100-1 (Plastic Low Profile Quad Flat Package) Note: Dimensions in mm Data Sheet 82 ADM8515/X Packaging Rev. 1.21, 2005-11-08 ...
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... Ref. – – 0.20 0.27 0.50 BSC. 12.00 12.00 Tolerance of Form and Position 0.20 0.20 0.08 0.08 83 ADM8515/X Inch Min. Typ. – – 0.002 – 0.053 0.005 0.630 BSC. 0.551 BSC. 0.630 BSC. 0.551 BSC. 0.003 – 0.003 – 0° 3.5° 0° – 11° ...
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... The high byte of product ID. The length for manufacture string. The word offset address of manufacture string. The length for product string. The word offset address of product string. The length for serial number string. The word offset address of serial number string. 84 ADM8515/X Appendix Rev. 1.21, 2005-11-08 ...
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... Product string length 1E bytes Product string starts from word offset Serial number string length 0A bytes Serial number string starts from word offset 38 offset 0E:descriptor size 14 bytes 03: string descriptor 41........: UNICODE encoded string 85 ADM8515/X Appendix , thus byte H , thus byte offset H , thus byte H Rev. 1.21, 2005-11-08 ...
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... Offset (byte) Value 30- 0020 00................ 50- 0031 00 Data Sheet Description 1E:descriptor size 30 bytes 03: string descriptor 55........: UNICODE encoded string 0A: descriptor size 10 bytes 03: string descriptor 30........: UNICODE encoded string 86 ADM8515/X Appendix Rev. 1.21, 2005-11-08 ...
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... Latch High LQFP Low Profile Quad Flat Package LS Least Significant Bit M MAC Media Access Controller MDC Management Data Clock MDIO Management Data Input/Output MFG Manufacture Program MII Media Independent Interface N NAK Not Acknowledge NLP Normal Link Pulse Data Sheet 87 ADM8515/X Rev. 1.21, 2005-11-08 ...
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... Transmit Clock TXD Transmit Data TXIN Transmit Input Negative TXIP Transmit Input Positive U USB Universal Serial Bus UTMI USB 2.0 Transceiver Macrocell Interface V VDD Voltage VIN Voltage In VOUT Voltage out W WAN Wide Area Network X XCVR Transceiver xDSL A/S/V DSL Data Sheet 88 ADM8515/X Rev. 1.21, 2005-11-08 ...
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