sta013b STMicroelectronics, sta013b Datasheet - Page 15

• Manufacturer Part Number: sta013b
• Description: Mpeg 2.5 Layer Iii Audio Decoder
• Manufacturer: STMicroelectronics

MUTE
Address: 0x14
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
DATA_REQ_ENABLE
Address: 0x18
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
SYNCSTATUS
Address: 0x40
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
MSB
MSB
b7
b7
X
X
X
b6
X
b6
b6
X
X
X
b5
X
b4
X
b5
b5
X
X
X
b3
X
b4
b4
X
X
X
b2
X
b1
b3
b3
X
X
X
X
LSB
b0
0
1
b2
b2
X
0
1
CMD_INTERRUPT
Address: 0x16
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care;
0 = normal operation;
1 = write into I
The INTERRUPT is used to give STA013 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x59 ... 0x5D). Every time the
Master has to extract the new buffer content (5
bytes) it writes into this register, setting it to a
non-zero value.
mode.
The buffered Output Clock has the same fre-
quency than the input clock (XTI)
MSB
b7
SS1
X
b1
b1
X
X
0
0
1
1
b6
X
LSB
LSB
SS0
b0
b0
X
X
0
1
0
1
STA013 - STA013B - STA013T
2
b5
X
C/Ancillary Data
b4
X
Research of sync word
Wait for Confirmation
buffered output clock
b3
X
request signal
Synchronised
Description
Description
not used
b2
X
b1
X
LSB
15/38
b0
0
1