lm25061pmmx-2 National Semiconductor Corporation, lm25061pmmx-2 Datasheet - Page 14

• Manufacturer Part Number: lm25061pmmx-2
• Description: Positive Low Voltage Power Limiting Hot Swap Controller
• Manufacturer: National Semiconductor Corporation

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MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection
be based on the following criteria:
-
system voltage (V
occur at V
inserted or removed.
-
on the current limit threshold (50 mV/R
load current, since the circuit can operate near the current
limit threshold continuously.
The maximum continuous current rating should be based
The BV
FIGURE 9. Load Draws Current During Turn-On
FIGURE 8. No Load Current During Turn-On
SYS
DSS
when the circuit card, or adjacent cards, are
rating should be greater than the maximum
SYS
), plus ringing and transients which can
S
), not the maximum
FIGURE 10. MOSFET Power Up Waveforms
30090322
30090323
14
B) Turn-on with power limit and current limit: The maxi-
mum allowed power dissipation in Q1 (P
the resistor at the PWR pin, and the current sense resistor
R
threshold (I
limit threshold at maximum V
erates initially in the power limit mode when the V
high, and then transitions to current limit mode as the current
increases to I
suming the load (R
for the output voltage to reach its final value is approximately
equal to:
For example, if V
P
current level (I
Period must be set longer than t
-
the current threshold for the circuit breaker function (95 mV/
R
-
the thermal properties, should be used to determine the max-
imum power dissipation threshold set by the R
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM25061-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
FET(LIM)
S
S
. See the Power Limit Threshold section. If the current limit
).
The Pulsed Drain Current spec (I
The SOA (Safe Operating Area) chart of the device, and
= 10W, t
LIM
) is higher than the current defined by the power
LIM
P
) is approximately 0.83A. The Fault Timeout
and V
SYS
ON
L
) is not connected during turn-on, the time
calculates to
= 12V, C
DS
decreases. See Figure 10b. As-
DS
(P
L
ON
= 1000 µF, I
FET(LIM)/
.
≊
DM
12.2 ms, and the initial
) must be greater than
FET(LIM)
V
SYS
30090325
) the circuit op-
LIM
) is defined by
PWR
DS
= 1A, and
resistor.
of Q1 is