SY10 Raltron, SY10 Datasheet - Page 7

• Manufacturer Part Number: SY10
• Manufacturer: Raltron

11) (FREQ&PHASE_LOCKING)
The path 11 runs until the frequency acquisition or the phase locking is in progress with no changes at control pins.
The module goes through a few intermediate states in order to accomplish phase tracking. There are three basic
intermediate steps that include frequency acquiring, phase acquisition and tracking. Tracking can have additional
steps depending of the bandwidth to be achieved.
12) (HOLDOVER)
The path 12 runs until the holdover mode is in progress with no changes at control signals.
13) (FREQ&PHASE_LOCKING_ HOLDOVER)
The path 13 runs in following conditions:
14) (FREERUN_HOLDOVER)
The path 14 runs only if the control signals were changed to one (0011) and valid history buffer for holdover
operation is available – the holdover mode was selected.
SY10 Master-Slave Operation – Secondary PLL
In systems where clock redundancy is required it is possible to connect two SY10 – such connection shown at the
figure below. The module has two pins dedicated for this feature – MS/FR and SEC IN. The MS/FR control input
selects if the module will operate as master (logic high) or slave in the system. The SEC IN is input for signal that
comes from another clock module. In the system always clock “one” operates as master and the second one as
slave clock. When operating as a slave the output of SY10 also tracks the master so it provides minimum phase
difference between the two clocks. This is very useful as it makes easier “hitless” switching of references. The
Master-Slave control can also be done using SPI communication setting the bit MS in register CFGREG1. Please
see more in Memory Mapped Registers section. The typical Master-Slave connection block diagram is show on
figure below.
The state machine of SY10 Master –Slave operation module can be controlled using one of two interfaces:
After the reset the module is set to use the external control pin for control function but user can change it by setting
bit UI in register CFG1. By setting the UI bit to 1 the module ignores states of the control pins and use bits in CFG1
1) if the used reference was lost or was detected bad,
2) if the control signals were changed to one (0011) – the holdover mode was selected.
3) one external control pin MS/FR.
4) setting MS bit in CFG1 register using serial peripheral interface (SPI).
Tel: [phone] § Fax: [phone] § e-mail: [e-mail] § Internet: http://www.raltron.com
RALTRON ELECTRONICS CORP. § 10651 N.W.19
M/S
M/S
Figure 3. - The Master – Slave connection of two SY10.
SY10
SY10
1
2
OUT (Pin 10)
OUT (Pin 10)
SEC IN (Pin 25)
SEC IN (Pin 25)
th
St § Florida 33172 § U.S.A.
STRATUM 3/3E CLOCK UNIT – SY10
SYNCHRONOUS EQUIPMENT
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