adg1211 Analog Devices, Inc., adg1211 Datasheet

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adg1211

Manufacturer Part Number
adg1211
Description
Low Capacitance, Low Charge Injection, ?15 V/+12 V Icmos? Quad Spst Switches
Manufacturer
Analog Devices, Inc.
Datasheet

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FEATURES
1 pF off capacitance
2.6 pF on capacitance
<1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V, +12 V
No V
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP
Typical power consumption: <0.03 μW
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1211/ADG1212/ADG1213 are monolithic complemen-
tary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an iCMOS
(industrial CMOS) process. iCMOS is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage parts has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
L
supply required
±15 V/+12 V iCMOS
Low Capacitance, Low Charge Injection,
IN4
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on
the other two switches. The ADG1213 exhibits break-before-
make switching action for use in multiplexer applications.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
IN2
IN3
IN1
Ultralow capacitance.
<1 pC charge injection.
3 V logic-compatible digital inputs: V
No V
Ultralow power dissipation: <0.03 μW.
16-lead TSSOP and 3 mm × 3 mm LFCSP packages.
ADG1211/ADG1212/ADG1213
ADG1211
L
logic power supply required.
FUNCTIONAL BLOCK DIAGRAM
SWITCHES SHOWN FOR A LOGIC 1 INPUT
S1
D1
S2
D2
S3
D3
D4
S4
© 2005 Analog Devices, Inc. All rights reserved.
IN2
IN3
IN4
IN1
Quad SPST Switches
ADG1212
Figure 1.
S1
D1
S2
D2
D3
D4
S3
S4
IH
IN2
IN3
IN4
IN1
= 2.0 V, V
www.analog.com
ADG1213
IL
= 0.8 V.
S1
D1
S2
D2
S3
D3
S4
D4

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adg1211 Summary of contents

Page 1

... Logic 1 is required for the ADG1212. The ADG1213 has two switches with digital control logic similar to that of the ADG1211; the logic is inverted on the other two switches. The ADG1213 exhibits break-before- make switching action for use in multiplexer applications. ...

Page 2

... ADG1211/ADG1212/ADG1213 TABLE OF CONTENTS Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 REVISION HISTORY 7/05—Revision 0: Initial Version Terminology .......................................................................................8 Typical Performance Characteristics ..............................................9 Test Circuits..................................................................................... 12 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 15 Rev Page ...

Page 3

... Rev Page ADG1211/ADG1212/ADG1213 Unit Test Conditions/Comments V Ω typ V = ± −1 mA; Figure Ω max V = +13 −13 Ω typ V = ± − Ω max Ω typ V = − ...

Page 4

... ADG1211/ADG1212/ADG1213 Parameter POWER REQUIREMENTS Temperature range for Y version is −40°C to +125° Guaranteed by design, not subject to production test Version −40°C to −40°C to 25°C +85°C +125°C 0.001 1.0 220 320 0.001 1.0 0.001 1.0 Rev Page ...

Page 5

... Rev Page ADG1211/ADG1212/ADG1213 Unit Test Conditions/Comments V Ω typ −1 mA; Figure Ω max Ω typ − Ω max Ω typ ...

Page 6

... Exposure to absolute + 0 maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may applied at any one time. Table 4. ADG1211/ADG1212 Truth Table ADG1211 INx 0 1 Table 5. ADG1213 Truth Table ADG1213 INx 0 1 Rev ...

Page 7

... Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Rev Page ADG1211/ADG1212/ADG1213 ADG1211/ADG1212/ADG1213 PIN 1 INDICATOR ...

Page 8

... ADG1211/ADG1212/ADG1213 TERMINOLOGY I DD The positive supply current The negative supply current The analog voltage on Terminals D and The ohmic resistance between D and S. R FLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range ...

Page 9

... Dual Supply Figure 8. On Resistance as a Function 12V = for Single Supply Figure 9. Leakage Currents as a Function of Temperature, Dual Supply D S Rev Page ADG1211/ADG1212/ADG1213 250 V = +15V –15V SS 200 T = +125°C A 150 T = +85°C A ...

Page 10

... ADG1211/ADG1212/ADG1213 0. 12V 0. 1V/10V BIAS 0.20 0.15 0.10 0.05 0 –0.05 –0. TEMPERATURE (°C) Figure 10. Leakage Currents as a Function of Temperature, Single Supply +12V LOGIC, IN (V) X Figure 11. I vs. Logic Level DD 6 SOURCE TO DRAIN DRAIN TO SOURCE T = +25°C ...

Page 11

... Figure 18. Capacitance vs. Source Voltage, Dual Supply 4 3 3.0 2.5 2.0 1.5 1.0 0.5 0 100k 0 Figure 19. Capacitance vs. Source Voltage, Single Supply Rev Page ADG1211/ADG1212/ADG1213 SOURCE/DRAIN ON = +15V = –15V = +25°C DRAIN OFF SOURCE OFF –6 –4 – (V) BIAS = 12V = 0V = 25°C SOURCE/DRAIN ON ...

Page 12

... Figure 24. Test Circuit 5—Break-Before-Make Time Delay ADG1212 OUT ADG1211 IN 1nF V OUT GND Figure 25. Test Circuit 6—Charge Injection Rev Page (OFF CONNECT Figure 22. Test Circuit 3—On Leakage 50% 50% 50% ...

Page 13

... 50Ω V OUT 0.1μF 0.1μ 50Ω OUT V S Rev Page ADG1211/ADG1212/ADG1213 0.1μF NETWORK V V ANALYZER 50Ω OUT R L 50Ω GND V WITH SWITCH OUT INSERTION LOSS = 20 LOG V WITHOUT SWITCH OUT Figure 28. Test Circuit 9— ...

Page 14

... ADG1211/ADG1212/ADG1213 OUTLINE DIMENSIONS 0.15 0.05 PIN 1 INDICATOR 12° MAX 0.90 0.85 0.80 SEATING PLANE 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0° 0.65 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 3.00 0.60 MAX BSC SQ 0.45 12 2.75 TOP BSC SQ VIEW 9 0 ...

Page 15

... ADG1211YRUZ −40°C to +125°C 1 ADG1211YRUZ-REEL −40°C to +125°C 1 ADG1211YRUZ-REEL7 −40°C to +125°C 1 ADG1211YCPZ-500RL7 −40°C to +125°C 1 ADG1211YCPZ-REEL7 −40°C to +125°C 1 ADG1212YRUZ −40°C to +125°C 1 ADG1212YRUZ-REEL −40°C to +125°C 1 ADG1212YRUZ-REEL7 −40°C to +125°C 1 ADG1212YCPZ-500RL7 − ...

Page 16

... ADG1211/ADG1212/ADG1213 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04778–0–7/05(0) Rev Page ...

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