tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 64

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.2 Interrupt Latches (IL25 to IL3)
3. Interrupt Control Circuit
RA003
3.2 Interrupt Latches (IL25 to IL3)
tion execution interrupt. When an interrupt request is generated, the latch is set to "1", and the CPU is requested to
accept the interrupt if its acceptance is enabled. The interrupt latch is cleared to "0" immediately after the interrupt is
accepted. All interrupt latches are initialized to "0" during reset.
cleared to "0" individually by an instruction. However, IL2 and IL3 interrupt latches cannot be cleared by instruc-
tions.
clear interrupt requests generated while the instruction is executed.
ing clearing of the interrupt latch, and not setting the interrupt latch.
An interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruc-
The interrupt latches are located at addresses 0x0FE0, 0x0FE1, 0x0FE2, 0x0FE3 in SFR area. Each latch can be
Do not use any read-modify-write instruction, such as a bit manipulation or operation instruction, because it may
Interrupt latches cannot be set to "1" by using an instruction. Writing "1" to an interrupt latch is equivalent to deny-
Since interrupt latches can be read by instructions, the status of interrupt requests can be monitored by software.
Note: In the main program, before manipulating an interrupt latch (IL), be sure to clear the master enable flag (IMF) to "0"
(Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI
instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. How-
ever, if using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1".
Example 1: Clears interrupt latches
Example 2: Reads interrupt latches
Example 3: Tests interrupt latches
DI
LD
LD
EI
LD
TEST
JR
(ILL), 0y00111111
(ILH), 0y11101000
WA, (ILL)
(ILL). 7
F, SSET
Page 50
; IMF m 0
; IL7 to IL6 m 0
; IL12, IL10 to IL8 m 0
; IMF m 1
; W m ILH, A m ILL
; if IL7=1 then jump
;
TMP89FM42