tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 90

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.3 Functions
5. Watchdog Timer (WDT)
RA000
5.3.2 Setting the clear time of the 8-bit up counter
When WDCTR<WDTW> is 00
When WDCTR<WDTW> is 01
When WDCTR<WDTW> is 10
When WDCTR<WDTW> is 11
5.3.3 Setting the overflow time of the 8-bit up counter
8-bit up counter value
8-bit up counter can be cleared at any time.
time of the 8-bit up counter. If the operation for releasing the 8-bit up counter is attempted outside the clear
time, a watchdog timer interrupt request signal occurs.
within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs
due to the overflow, depending on the WDCTR<WDTOUT> setting.
request signal occurs, depending on the WDCTR<WDTOUT> setting.
counter continues counting, even after the overflow has occurred.
SLEEP mode, and restarts counting up after the STOP/IDLE/SLEEP mode is released. To prevent the 8-bit up
counter from overflowing immediately after the STOP/IDLE/SLEEP mode is released, it is recommended to
clear the 8-bit up counter before the operation mode is changed.
Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore, the first
WDCTR<WDTW> sets the clear time of the 8-bit up counter.
When WDCTR<WDTW> is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the
When WDCTR<WDTW> is not "00", the clear time is fixed to only a certain period within the overflow
At this time, the watchdog timer is not cleared but continues counting. If the 8-bit up counter is not cleared
WDCTR<WDTT> sets the overflow time of the 8-bit up counter.
When the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt
If the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog
The watchdog timer temporarily stops counting up in the STOP mode (including warm-up) or in the IDLE/
Figure 5-3 WDCTR<WDTW> and the 8-bit up Counter Clear Time
overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a maximum of 1
source clock. The 8-bit up counter must be cleared within the period of the overflow time minus 1 source clock
cycle.
Table 5-1 Watchdog Timer Overflow Time (fcgck=10.0 MHz; fs=32.768 kHz)
WDTT
00
01
10
11
FFH
00H 01H
Outside the clear time
DV9CK = 0
104.86 m
419.43 m
26.21 m
1.678
Outside the clear time
NORMAL mode
3FH 40H
Watchdog timer overflow time [s]
Page 76
Outside the clear time
Clear time
DV9CK = 1
250.00 m
62.50 m
1.000
4.000
7FH 80H
Clear time
250.00 m
62.50 m
SLOW
mode
1.000
4.000
BFH C0H
Clear time
Clear time
TMP89FM42
FFH 00H