lnbeh21 STMicroelectronics, lnbeh21 Datasheet - Page 6

• Manufacturer Part Number: lnbeh21
• Description: Lnb Supply And Control Ic With Step-up Converter And Ic Interface
• Manufacturer: STMicroelectronics

LNBEH21
DATA VALIDITY
As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
START AND STOP CONDITIONS
As shown in fig. 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must
be sent before each START condition.
BYTE FORMAT
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
6). The peripheral (LNBEH21) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which
has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA
line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBEH21 won't generate the
acknowledge if the V
supply is below the Undervoltage Lockout threshold (6.7V typ.)
CC
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the LNBEH21, the µP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking and decreases the noise immunity.
2
Figure 4: Data Validity On The I
C Bus
2
Figure 5: Timing Diagram On I
C Bus
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