pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 363
pxf4336
Manufacturer Part Number
pxf4336
Description
Abm Premium Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4336.pdf
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Register 118 IMRU
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
IMRU(15:0)
Data Sheet
15
7
Interrupt Mask Register Upstream
14
Interrupt Mask Upstream
Each bit controls whether the corresponding interrupt indication in
register ISRU (same bit location) activates the interrupt signal:
1
0
6
Read/Write
0000
IMRU
Written by CPU to control interrupt signal effective
events
H
13
5
Interrupt indication masked.
The interrupt signal is not activated upon this event.
Interrupt indication unmasked.
The interrupt signal is activated upon this event.
E6
H
12
IMRU(15:8)
4
IMRU(7:0)
363
11
3
10
2
Register Description
PXF 4336 V1.1
9
1
2001-12-17
ABM-P
8
0
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