at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 173

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

21.9.2
Figure 21-17.
6384B–ATARM–15-Dec-08
Early Read Wait State
Figure 21-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
NBS0, NBS1,
NBS2, NBS3,
A0,A1
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD =
time
signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode
21-19). The write operation must end with a NCS rising edge. Without an Early Read Wait
State, the write operation could not complete properly.
0), the feedback of the write control signal is used to control address, data, chip select and
byte select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See
A[25:2]
D[31:0]
NCS0
NCS2
NWE
MCK
NRD
(Figure
NCS2
21-18).
NRD_CYCLE
Figure
21-20.
AT91SAM9G20 Preliminary
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
(Figure
173