at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 304
at91sam9g20-cu
Manufacturer Part Number
at91sam9g20-cu
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9G20-CU.pdf
(814 pages)
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26.9.10
Register Name:CKGR_PLLBR
Access Type:Read-write
Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
• DIVB: Divider B
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLL B Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULB: PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 62 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USBDIV: Divider for USB Clock.
304
DIVB
0
1
2 - 255
0
0
1
1
31
23
15
–
–
7
AT91SAM9G20 Preliminary
PMC Clock Generator PLL B Register
OUTB
USBDIV
0
1
0
1
30
22
14
–
–
6
29
21
13
5
USBDIV
Divider Selected
Divider output is PLL B clock output
Divider output is PLL B clock output divided by 2
Divider output is PLL B clock output divided by 4
Reserved
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVB.
28
20
12
4
DIVB
27
19
11
–
3
PLLBCOUNT
MULB
26
18
10
–
2
25
17
–
9
1
6384B–ATARM–15-Dec-08
24
16
–
8
0
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