at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 535
at91sam9g20-cu
Manufacturer Part Number
at91sam9g20-cu
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9G20-CU.pdf
(814 pages)
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• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection
0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
6384B–ATARM–15-Dec-08
0x9-0xF
START
CKG
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
None, continuous clock
Receive Clock enabled only if RF Low
Receive Clock enabled only if RF High
Reserved
Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
Transmit start
Detection of a low level on RF signal
Detection of a high level on RF signal
Detection of a falling edge on RF signal
Detection of a rising edge on RF signal
Detection of any level change on RF signal
Detection of any edge on RF signal
Compare 0
Reserved
Receive Clock Gating
Receive Start
AT91SAM9G20 Preliminary
535
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