atxmega192a1-au ATMEL Corporation, atxmega192a1-au Datasheet - Page 102

• Manufacturer Part Number: atxmega192a1-au
• Description: 8/16-bit Xmega A1 Microcontroller
• Manufacturer: ATMEL Corporation

8067M–AVR–09/10
9. EEPROM erase and write does not work with all System Clock sources
10. BOD will be enabled after any reset
11. Propagation delay analog Comparator increasing to 2 ms at -40 °C
12. Sampled BOD in Active mode will cause noise when bandgap is used as reference
13. Default setting for SDRAM refresh period too low
14. Flash Power Reduction Mode can not be enabled when entering sleep mode
When doing EEPROM erase or Write operations with other clock sources than the 2 MHz
RCOSC, Flash will be read wrongly for one or two clock cycles at the end of the EEPROM
operation.
Problem fix/Workaround
Alt 1: Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM.
Alt 2: Ensure to be in sleep mode while completing erase or write on EEPROM. After starting
erase or write operations on EEPROM, other interrupts should be disabled and the device
put to sleep.
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
When the analog comparator is used at temperatures reaching down to -40 °C, the propaga-
tion delay will increase to ~2 ms.
Problem fix/Workaround
None
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC and DAC.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC or the DAC, the BOD must not be set
in sampled mode.
If the SDRAM refresh period is set to a value less then 0x20, the SDRAM content may be
corrupted when accessing through On-Chip Debug sessions.
Problem fix/Workaround
The SDRAM refresh period (REFRESHH/L) should not be set to a value less then 0x20.
If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby
sleep mode, the device will only wake up on every fourth wake-up request.
If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time
will vary with up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
XMEGA A1
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