p80c52x2 NXP Semiconductors, p80c52x2 Datasheet - Page 3
p80c52x2
Manufacturer Part Number
p80c52x2
Description
80c51 8-bit Microcontroller Family 4k/8k/16k/32k Rom/otp 128b/256b Ram
Manufacturer
NXP Semiconductors
Datasheet
1.P80C52X2.pdf
(62 pages)
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Philips Semiconductors
FEATURES
2003 Jan 24
80C51 Central Processing Unit
– 4 kbytes ROM/EPROM (P80/P87C51X2)
– 8 kbytes ROM/EPROM (P80/P87C52X2)
– 16 kbytes ROM/EPROM (P80/P87C54X2)
– 32 kbytes ROM/EPROM (P80/P87C58X2)
– 128 byte RAM (P80/P87C51X2 and P80C31X2)
– 256 byte RAM (P80/P87C52/54X2/58X2 and P80C32X2)
– Boolean processor
– Fully static operation
– Low voltage (2.7 V to 5.5 V at 16 MHz) operation
12-clock operation with selectable 6-clock operation (via software
or via parallel programmer)
Memory addressing capability
– Up to 64 kbytes ROM and 64 kbytes RAM
Power control modes:
– Clock can be stopped and resumed
– Idle mode
– Power-down mode
CMOS and TTL compatible
Two speed ranges at V
– 0 to 30 MHz with 6-clock operation
– 0 to 33 MHz with 12-clock operation
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
CC
= 5 V
3
PLCC, DIP, TSSOP or LQFP packages
Extended temperature ranges
Dual Data Pointers
Security bits:
– ROM (2 bits)
– OTP (3 bits)
Encryption array - 64 bytes
Four interrupt priority levels
Six interrupt sources
Four 8-bit I/O ports
Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
Programmable clock-out pin
Asynchronous port reset
Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock
mode)
Wake-up from Power Down by an external interrupt.
P80C3xX2; P80C5xX2;
P87C5xX2
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