mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 79

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

System on a Chip Guide — 9S12UF32DGV1/D V01.05
4.2.1 Normal Operating Modes
These modes provide three operating configurations: Normal Single-Chip Mode, Normal Expanded Wide
Mode, and Normal Expanded Narrow Mode. Background debug (BDM) is available in all three normal
modes, but must first be enabled for some operations by means of a BDM background command, then
activated.
4.2.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. Ports A and B are general purpose I/O pins, initially
configured as high-impedance inputs with their internal pull-ups disabled. Port pins PE[7:2] are general
purpose I/O pins, and port pins PE[1:0] are available as general purpose input only pins. All of Port E pins
are initially configured as high-impedance inputs with internal pull-ups enabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in normal single chip mode. In normal single chip mode, the
associated control bits PIPOE, LSTRE, and RDWE are reset to zero, and writing a one to them in this mode
does not change the operation of the associated Port E pins.
In normal single chip mode, the MODE register is writable one time. This allows a user program to change
the bus mode to special single chip or normal expanded wide or normal expanded narrow modes and/or
turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running ECLK output by clearing NECLK=0. Typically the only
use for an ECLK output while the MCU is in normal single chip mode would be to get a constant speed
clock for use in the external application system.
4.2.1.2 Normal Expanded Wide Mode
In normal expanded wide mode, Ports A and B are configured as a 16-bit multiplexed address and data bus
and Port PE4 is configured as the ECLK output signal. These signals allow external memory and
peripheral devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance
inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in the PEAR
register, but it would be unusual to do so in this mode. Development systems where pipe status signals are
monitored would typically use the special variation of this mode.
The Port E bit 2 pin can be re-configured as the R/W bus control signal by writing “1” to the RDWE bit
in the PEAR register. If the expanded system includes external devices that can be written, such as RAM,
the RDWE bit would need to be set before any attempt to write to an external location. If there are no
writable resources in the external system, PE2 can be left as a general purpose I/O pin.
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