w79e532 Winbond Electronics Corp America, w79e532 Datasheet - Page 17

• Manufacturer Part Number: w79e532
• Description: 8-bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

ISP Control Register
SWRST/HWB: Set this bit to launch a whole device reset that is same as asserting high to RST pin,
LDAP: This bit is Read Only. High: device is executing the program in LDFlash. Low: device is
LDSEL: Loader program residence selection. Set to high to route the device fetching code from
ENP: In System Programming Mode Enable. Set this be to launch the ISP mode. Device will operate
Software Reset
Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFlash after time
out.
Port 2
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
Port 4 Chip-select Polarity
P4xINV: The active polarity of P4.x when set it as chip-select signal. High = Active High. Low = Active
P0UP: Enable Port 0 weak pull up.
ISP procedures, such as Erase, Program and Read operations, according to correlative SFRs
settings. During ISP mode, device achieves ISP operations by the way of IDLE state. In the
other words, device is not indeed in IDLE mode is set bit PCON.1 while ISP is enabled. Clear
this bit to disable ISP mode, device get back to normal operation including IDLE state.
executing the program in APFlashs.
address bits for accesses to external memory.
LDFlash.
Low.
Mnemonic: P2
Mnemonic: P4CSIN
Mnemonic: CHPCON
micro controller will be back to initial state and clear this bit automatically. To read this
bit, its alternate function to indicate the ISP hardware reboot mode is invoking when
read it in high.
Bit:
Bit:
Bit:
SWRST/HWB
P43INV P42INV P42INV P40INV
P2.7
7
7
7
P2.6
6
6
6
-
LDAP
P2.5
5
5
5
- 17 -
P2.4
4
4
4
-
Publication Release Date: November 21, 2005
P2.3
W79E532/W79L532
3
3
3
-
-
Address: A0h
Address: A2h
Address: 9Fh
P2.2
2
2
2
-
-
LDSEL
P2.1
1
1
1
-
Revision A5
P0UP
ENP
P2.0
0
0
0