w79e532 Winbond Electronics Corp America, w79e532 Datasheet - Page 24

• Manufacturer Part Number: w79e532
• Description: 8-bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

OV:
F1:
P:
Watchdog Control
POR:
WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a
EWT:
RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed
Access procedure to write. The remaining bits have unrestricted write accesses. Please refer TA
register description.
TA
WDCON
CKCON
Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read
or written by software. A write by software is the only way to clear this bit once it is set.
to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit
indicates that the time-out period has elapsed. This bit must be cleared by software.
reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit.
This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer
will have no affect on this bit.
helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog
timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
User Flag 1: General purpose flag that can be set or cleared by the user by software.
Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.
MOV TA, #AAH
MOV TA, #55H
SETB WDCON.0
ORL CKCON, #11000000B
MOV TA, #AAH
RS1
Mnemonic: WDCON
0
0
1
1
EG
REG
REG
Bit:
RS0
0
1
0
1
C7H
D8H
8EH
7
-
Register bank
POR
6
0
1
2
3
; Reset watchdog timer
; Select 26 bits watchdog timer
- 24 -
5
-
Address
00-07h
08-0Fh
10-17h
18-1Fh
4
-
WDIF
W79E532/W79L532
3
Address: D8h
WTRF
2
EWT
1
RWT
0