xr16v2750 Exar Corporation, xr16v2750 Datasheet - Page 35

• Manufacturer Part Number: xr16v2750
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.3
EMSR[6]: LSR Interrupt Mode
•
•
EMSR[7]: 16X Sampling Rate Mode
Logic 0 = 8X Sampling Rate.
Logic 1 = 16X Sampling Rate (default).
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD/16 to achieve the fractional baud rate divisor. DLD must be enabled
via EFR bit-4 before it can be accessed.
FRACTIONAL DIVISOR” ON PAGE 11.
This register contains the device ID (0x0A for XR16V2750). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
User Programmable Transmit/Receive Trigger Level Register. If both the programmable TX and RX trigger
levels are used, the TX trigger levels must be set before the RX trigger levels.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.12
4.13
4.14
4.15
4.16
4.17
Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
FIFO Level Register (FLVL) - Read-Only
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Trigger Level Register (TRG) - Write-Only
RX/TX FIFO Level Count Register (FC) - Read-Only
for details.
EMSR
B
IT
1
1
1
1
1
1
1
1
-5
T
ABLE
EMSR
B
IT
0
0
0
0
1
1
1
1
-4
13: A
SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
FCTR
B
UTO
IT
0
0
1
1
0
0
1
1
-1
35
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
RTS H
FCTR
B
IT
0
1
0
1
0
1
0
1
YSTERESIS
-0
(C
H
HARACTERS
YSTERESIS
RTS#
±40
±44
±48
±52
±12
±20
±28
±36
)
XR16V2750