spear-09-b042 STMicroelectronics, spear-09-b042 Datasheet - Page 30

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spear-09-b042

Manufacturer Part Number
spear-09-b042
Description
Spear?? Basic Arm 926ej-s Core, Customizable Logic, Large Ip Portfolio Soc
Manufacturer
STMicroelectronics
Datasheet

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Cryptographic co-processor (C3)
SPEAr BASIC has an hardware cryptographic co-processor with the following features:
Low jitter PLL
Within the USB Hosts and device a local low jitter PLL is provided to meet the USB2.0
specification requirements.
Main PLL
Two PLLs are provided so that the external memory bus can run at a different frequency to
the internal AHB. To reduce the system emission both the PLL are offering four operational
modes:
Supported cryptographic algorithms:
Instruction driven DMA based programmable engine.
AHB master port for data access from/to system memory.
AHB slave port for co-processor register accesses and initial engine-setup.
The co-processor is fully autonomous (DMA input reading, cryptographic operation
execution, DMA output writing) after being set up by the host processor.
The co-processor executes programs written by the host in memory, it can execute an
unlimited list of programs.
The co-processor supports hardware chaining of cryptographic blocks for optimized
execution of data-flow requiring multiple algorithms processing over the same set of
data (for example encryption + hashing on the fly).
Normal mode
Fractional mode
Double side dithering mode
Single side dithering mode
Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes.
Data encryption standard (DES) cipher in ECB and CBC modes.
SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.
SPEAR-09-B042

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