isppac30 Lattice Semiconductor Corp., isppac30 Datasheet
isppac30
Related parts for isppac30
isppac30 Summary of contents
Page 1
... The flexibility of ISP enables programming, verifi- cation and unlimited reconfiguration, directly on the printed circuit board. The ispPAC30 is a complete front end solution for data acquisition applications using 10 to 12-bit ADC's. It pro- vides multiple single-ended or differential signal inputs, multiplexing, precision gain, offset adjustment, filtering, and comparison functionality ...
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... C to +85° 10kHz Nominally 2.500V LOAD (VREF change = -1%) source OUT (VREF change = +1%) sink OUT -40 to +85°C 100kHz bandwidth 1kHz 10mV overdrive 100mV overdrive 2.8V overload 2 ispPAC30 Data Sheet Min. Typ. Max. Units 0 2 100 µ µV/° Ω ...
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... All gains, minimum feedback capacitor All gains All gains 4V output step, low to high 4V output step, high to low R = 1kΩ 10kHz L IN Deviation from calculated -3db point -40° +85°C 3 ispPAC30 Data Sheet Min. Typ. Max. Units 7+sign bits 0.25 0.5 lsb -1 lsb 3 mV ...
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... -1.0mA OH 2 For E CMOS cells Initial turn on Subsequent user initiated 5.0V S Time to resume normal operation x Gain = 5V). When G=1, the maximum single IN 4 ispPAC30 Data Sheet Min. Typ. Max. Units 10 µA ±50 µ A 250 mV 0.4 V 2.4 V 10K 1M cycles 140 250 ms 50 100 4 ...
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... PD Power Down VS Supply Voltage GND Ground SCOM Signal Common NC No Connects 5 ispPAC30 Data Sheet Description Differential input pins, with two pins per input (e.g., IN2+ and IN2-). Each are components where differential IN+ Multiplexer logic input pin. Selects either of two analog channels to IA1 (instrument amplifi ...
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... Filter IA 16 Amplify Integrate Compare MDAC 17 18 MDAC Filter IA Amplify 21 Integrate Vref2 Compare 22 23 JTAG/SPI Auto-Calibration Interface Logic 24 & Configuration 2.5V Reference Memory ispPAC30 24-Pin SOIC ENSPI 10 TMS 9 TDO 8 TDI 7 TCK MSEL1 4 MSEL2 3 CAL GND ...
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... Lattice Semiconductor Part Number Description Device Family Device Number ispPAC30 Ordering Information ispPAC30-01PI ispPAC30-01SI Package Options ispPAC30 – Part Number 28-Pin PDIP 24-Pin SOIC 7 ispPAC30 Data Sheet Grade Blank = Commercial I = Industrial Package P = PDIP S = SOIC Performance Grade 01 = Standard Package 28-pin PDIP ...
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... TDO Delay Clock to Valid tdoxz TDO Delay Valid to Float calmin Minimum Calibration Pulse TCK TMS TDI TDO CAL Parameter Conditions tckmin tmss tmsh tdozx 8 ispPAC30 Data Sheet Min Typ — 80ns — 40ns — 40ns — 15ns — 4ns — 15ns — ...
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... TCK tencss ENSPI ttcsfs CS TDI TDO Parameter tckh tckl tckmin tcsfts tdis tdih LSB tdov LSB tdozx 9 ispPAC30 Data Sheet Min Typ Max 80ns 40ns 40ns 5ns 8ns 10ns 10ns 10ns 8ns 25ns 10ns 60ns 60ns 60ns 145ns 30ns …. ...
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... Executed in Run-Test/Idle Executed in Run-Test/Idle tpwp, tpwe tmss (PRGCFG/CLRALL executed in Run-Test/Idle state) Executed on rising edge of CAL (Note: CAL internally initiated at device turn-on.) tcalmin V OUT = 0V tpwcal1, tpwcal2 10 ispPAC30 Data Sheet Min Typ 80ms 80ms tmss Conditions Min Typ 140ms — 30ns 50ms Max ...
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... Frequency (Hz) Offset Voltage ( Wafer Lots PDIP Pkg 25 +25°C For All Gains, 20 Output Referred +1 Offset (mV) 11 ispPAC30 Data Sheet PSR vs. Frequency 100k 1M 100 1k 10k Frequency (Hz) Output Current Drive 75 Vout Forced to Nominal - 50mV 50 25 ...
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... Vin+ IA1 Vin- G=1 IA2 2.5V VREF1 1µS 0.625V Gain = 1 Load = 1k ; 600pF 1µS 20mV Gain = 1 Load = 1k ; 600pF Cfb=min OA1 Vout Large-Signal Vin+ 0.0 V 2.0 V 0.0 V Vin- 2.0 V 0.0 V 2.0 V VREF1 2.5 V 2.5 V 2.5 V Vout 0.5 V 4 ispPAC30 Data Sheet 1µS Ω 1µS Ω Small-Signal 0.00 V 0.05 V 0.00 V 0.05 V 0.00 V 0.05 V 2.5 V 2.5 V 2.5 V 2.45 V 2.55 V 2.45 V ...
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... Device Input Cells In an ispPAC30 device, any input pin can be routed to any of the four input instrument amplifiers (IA), two of which have dual input multiplexers either of the two multiplying DAC’s (MDAC), or any combination of these. In addi- tion, either output amplifier (OA) can be routed to any or all of these same input cells. This enables great flexibility in how an ispPAC30 is confi ...
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... MDACs. By selective combination of these various settings, a very large number of user control offset voltages can be summed with any input signal. This is also the basis of how the ispPAC30 can be configured as a comparator. With the output amplifier configured as a comparator, an unknown signal is summed with a precise ref- erence value and an input above or below that reference level will cause a change in state of the output compara- tor ...
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... Increasing MDAC Effective Resolution Because the value of the ispPAC30’s voltage references can be set to several output voltages, ranging from 64mV to 2.5V possible to use high-value MDAC settings (>50% full scale) to synthesize most desired thresholds. This means that a given threshold (32mV or greater) can be set with a resolution of +/-0.8%. ...
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... As mentioned in the previous IA section, any input voltage between 0 to 2.8V can be applied directly to an ispPAC30 input. To keep the output from trying to swing below 0V, if Vin- is more positive than Vin+, an offsetting signal must be applied to the appropriate summing node to balance or counteract the negative input. Single-ended connections, however, only require that the minus input be connected some other fi ...
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... used to reference a high impedance source (e.g., one that does not require more than 40µA), the VREF directly. An example is shifting the DC level of a signal connected to the input pin of an ispPAC30. Also, by using a current limiting resistor with the VREF ence ...
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... The feedback capacitance set is required to maintain necessary stability. When used in filter mode, the ispPAC30 differs from the wideband amplifier in that it has seven alternative feedback capacitor values available to form the lowpass filter corner frequencies. See Table 3 for these values (listed as the maximum corner frequencies in the precision fi ...
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... DC gain. This increase must be compensated for if the filter is to maintain unity gain from input to output. Because there are two MDACs in an ispPAC30, one way to do this is to attenuate the input signal through MDAC1 by the same amount the feedback signal is attenuated by MDAC2. To maintain signal polarity, however, MDAC1 should be set to a positive gain ...
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... In addition to full power-down mode, either of the output amplifiers can be shut down independently of all other cir- cuitry. This can be done at any time by setting internal E sumption while the rest of the ispPAC30 is in normal operation. This could also be accomplished at the time the device is programmed initially via dialog box commands available in the PAC-Designer software. Note: Any IA or MDAC that has nothing connected to its input is also automatically shut down. JTAG User Confi ...
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... Electronic Security Fuse Auto-Calibration Mode Every time the ispPAC30 is powered up, an automatic auto-calibration sequence is initiated. If this adversely affects system operation, provisions must be incorporated that minimize the result as auto-calibration cannot be defeated. The auto-calibration of the ispPAC30 effectively isolates it from external connections and drives the inputs of the device to 0V and checks to see that there is zero offset at the outputs ...
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... SPI mode can be enabled via the logic level setting of the ENSPI pin. To achieve full control of an ispPAC30, all possible bits used in configuration (112) must be set each time the configuration is updated. This full set of configuration bits is referred to as the CFG or confi ...
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... Lattice Semiconductor Figure 6. PAC-Designer Design Entry Screen PAC Designer - [ispPAC30.PAC: Schematic] File Edit View MSEL1 = 0 (a) IN1 IN2 IN3 IN4 MSEL2 = 0 (a) Ready Design Simulation Capability A powerful feature of PAC-Designer is its simulation capability, enabling quick and accurate verification of circuit operation and performance. Once a circuit is configured via the interactive design process, gain and phase response between any input and output can then be simulated. This function is part of the simulator capability which derives a transfer equation between the two points and then sweeps it over the user-specifi ...
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... IEEE Standard 1149.1 Interface Serial Port Programming Interface Communication with the ispPAC30 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispPAC30 as a serial programming interface, and not for boundary scan test purposes. 2 CMOS memory of the ispPAC30. This consists of 16 ...
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... A separate set of SRAM registers are pre- loaded at turn-on and determine the configuration of the ispPAC30 while it is under power. By cycling the TAP con- troller through the necessary states, data can also be shifted out of the configuration register to verify the current ispPAC30 confi ...
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... This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state Select-DR-Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- ispPAC30 Data Sheet 1 Select-IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- ...
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... TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC30. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard. With ispPAC30, any instruction beginning with a one will default to BYPASS. ...
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... JTAG and SPI device programming control of the ispPAC30 (specific bit assignments, word lengths, etc.). There are two unique load instructions specified by Lattice for the ispPAC30. They are the LATCHCFG (load CFG register) and RELOADCFG (load CFG from E ...
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... The POWERDN (power down command) and POWERUP (power up command) are unique instructions specified by Lattice for the ispPAC30 to command the normal and low-power or shut-down states of the device. As with other instructions above, these instructions do not begin until entry of the Run-Test/Idle state. Timing for coming out of power-down mode as well as supply current used in this mode are specifi ...
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... Lattice Semiconductor Package Diagrams 28-Pin PDIP (Dimensions in inches) 24-Pin SOIC (Dimensions in millimeters) ispPAC30 Data Sheet 30 ...