ht82a836r Holtek Semiconductor Inc., ht82a836r Datasheet - Page 35

• Manufacturer Part Number: ht82a836r
• Description: Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by two sources selected by configura-
tion option: its own self contained dedicated internal
WDT oscillator or f
tion option has been disabled, then any instruction relat-
ing to its operation will result in no operation.
The internal WDT oscillator has an approximate period
of 65 s at a supply voltage of 5V. If selected, it is first di-
vided by 256 via an 8-stage counter. Note that this pe-
riod can vary with VDD, temperature and process
variations. For longer WDT time-out periods the WDT
prescaler can be utilized. By writing the required value
to bits 0, 1 and 2 of the WDTS register, known as WS0,
WS1 and WS2, longer time-out periods can be
achieved. With WS0, WS1 and WS2 all equal to 1, the
division ratio is 1:128 which gives a maximum time-out
period.
A configuration option can select the instruction clock,
which is the system clock divided by 4, as the WDT clock
Rev. 1.00
SYS
/4. Note that if the WDT configura-
Watchdog Timer Register
35
source instead of the internal WDT oscillator. If the in-
struction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the sys-
tem cannot be restarted by the WDT and can only be re-
started using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
is therefore the recommended choice.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, only the Program Counter and
Stack Pointer will be reset. Three methods can be
adopted to clear the contents of the WDT and the WDT
prescaler. The first is an external hardware reset, which
means a low level on the RESET pin, the second is us-
ing the watchdog software instructions and the third is
via a HALT instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle CLR WDT instruction while the second is to use
the two commands CLR WDT1 and CLR WDT2 . For
the first option, a simple execution of CLR WDT will
clear the WDT while for the second option, both CLR
WDT1 and CLR WDT2 must both be executed to
successfully clear the WDT. Note that for this second
option, if CLR WDT1 is used to clear the WDT, succes-
sive executions of this instruction will have no effect,
only the execution of a CLR WDT2 instruction will
clear the WDT. Similarly, after the CLR WDT2 instruc-
tion has been executed, only a successive CLR WDT1
instruction can clear the Watchdog Timer.
HT82A836R
March 20, 2008