ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet - Page 38

• Manufacturer Part Number: ht82j30r
• Description: Ht82j30r/ht82j30a -- 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

In the Master Mode, the Master will always generate the
clock signal. The clock and data transmission will be ini-
tiated after data has been written to the SBDR register.
In the Slave Mode, the clock signal will be received from
an external master device for both data transmission or
reception. The following sequences show the order to
be followed for data transfer in both Master and Slave
Mode:
Rev. 1.10
Master Mode
Step 1. Select the clock source using the CKS bit in
Step 2. Setup the M0 and M1 bits in the SBCR control
Step 3. Setup the CSEN bit and setup the MLS bit to
Step 4. Setup the SBEN bit in the SBCR control
Step 5. For write operations: write the data to the
Step 6. Check the WCOL bit, if set high then a
Step 7. Check the TRF bit or wait for an SBI serial bus
Step 8. Read data from the SBDR register.
Step 9. Clear TRF.
Step10. Goto step 5.
Slave Mode:
Step 1. The CKS bit has a don t care value in the
Step 2. Setup the M0 and M1 bits to 00 to select the
Step 3. Setup the CSEN bit and setup the MLS bit to
Step 4. Setup the SBEN bit in the SBCR control
Step 5. For write operations: write data to the SBCR
the SBCR control register
register to select the Master Mode and the
required Baud rate. Values of 00, 01 or 10 can
be selected.
this must be same as the Slave device.
register to enable the SPI interface.
data into the TXRX buffer. Then use the SCK
Goto to step 6.For read operations: the data
in the TXRX buffer until all the data has been
collision error has occurred so return to step5.
If equal to zero then go to the following step.
interrupt.
this must be same as the Master device.
register to enable the SPI interface.
register, which will actually place the data into
the TXRX register, then wait for the master
choose if the data is MSB or LSB first,
SBDR register, which will actually place the
and SCS lines to output the data.
transferred in on the SDI line will be stored
received at which point it will be latched into
the SBDR register.
slave mode.
Slave Mode. The CKS bit is dont care.
choose if the data is MSB or LSB first,
clock and SCS signal. After this goto step 6.
38
SPI Configuration Options
Several configuration options exist for the SPI Interface
function which must be setup during device programming.
One option is to enable the operation of the WCOL, write
collision bit, in the SBCR register. Another option exists to
select the clock polarity of the SCK line. A configuration
option also exists to disable or enable the operation of the
CSEN bit in the SBCR register. If the configuration option
disables the CSEN bit then this bit cannot be used to affect
overall control of the SPI Interface.
Error Detection
The WCOL bit in the SBCR register is provided to indi-
cate errors during data transfer. The bit is set by the Se-
rial Interface but must be cleared by the application
program. This bit indicates a data collision has occurred
which happens if a write to the SBDR register takes
place during a data transfer operation and will prevent
the write operation from continuing. The bit will be set
high by the Serial Interface but has to be cleared by the
user application program. The overall function of the
WCOL bit can be disabled or enabled by a configuration
option.
Programming Considerations
When the device is placed into the Power Down Mode
note that data reception and transmission will continue.
The TRF bit is used to generate an interrupt when the
data has been transferred or received.
Step 6. Check the WCOL bit, if set high then a
Step 7. Check the TRF bit or wait for an SBI serial bus
Step 8. Read data from the SBDR register.
Step 9. Clear TRF
Step10. step 5
For read operations: the data transferred in
at which point it will be latched into the SBDR
collision error has occurred so return to step5.
If equal to zero then go to the following step.
interrupt.
on the SDI line will be stored in the TXRX
buffer until all the data has been received
register.
HT82J30R/HT82J30A
March 13, 2008