ak4673 AKM Semiconductor, Inc., ak4673 Datasheet - Page 46

• Manufacturer Part Number: ak4673
• Description: Stereo Codec With Mic/hp-amp And Touch Screen Controller
• Manufacturer: AKM Semiconductor, Inc.

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The ALC (Automatic Level Control) is executed by ALC block when ALC bit is “1”. When only DAC is powered-up,
ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC
circuit operates at recording path.
1. ALC Limiter Operation
During the ALC limiter operation, if either Lch or Rch exceeds the ALC limiter detection level
IVR values (same value) are attenuated automatically to the amount defined by the ALC limiter ATT step
IVL and IVR are then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level
28) or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
MS0670-E-01
PMADL bit, PMADR bit
ALC Operation
“01”, “10” or “11”
LMTH1
0
0
1
1
“00”
ZTM1
0
0
1
1
LMTH0
0
1
0
1
ZELMN
Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level
0
1
ZTM0
ALC Limier Detection Level
0
1
0
1
ALC Output ≥ −2.5dBFS
ALC Output ≥ −4.1dBFS
ALC Output ≥ −6.0dBFS
ALC Output ≥ −8.5dBFS
PMDAC bit
LMAT1
0
1
0
1
Table 29. ALC Limiter ATT Step (x: Don’t care)
Table 30. ALC Zero Crossing Timeout Period
0
0
1
1
x
1024/fs
128/fs
256/fs
512/fs
Table 27. ALC Setting (x: Don’t care)
LOOP bit
LMAT0
x
x
x
0
1
0
1
0
1
x
128ms
8kHz
16ms
32ms
64ms
Zero Crossing Timeout Period
- 46 -
Recording Monitor Playback
ALC Recovery Waiting Counter Reset Level
(Table
Recording & Playback
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
ALC Limiter ATT Step
−8.5dBFS > ALC Output ≥ −12dBFS
1 step
2 step
4 step
8 step
1step
Power-down
30).
Recording
Playback
16kHz
Status
16ms
32ms
64ms
8ms
0.375dB
0.750dB
1.500dB
3.000dB
0.375dB
44.1kHz
11.6ms
23.2ms
2.9ms
5.8ms
Recording path
Recording path
Recording path
(default)
Playback path
Power-down
(Table
ALC
(default)
28), the IVL and
(Table
(default)
[AK4673]
(default)
29). The
2007/10
(Table