ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 67

• Manufacturer Part Number: ak4671
• Description: Stereo Codec With Mic/rcv/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

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The ALC (Automatic Level Control) is executed by ALC block when ALC bit is “1”. ALC circuit operates at playback
path for Playback mode and operates at recording path for Recording mode as shown in
1. ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level
and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation
immediately (period: 1/fs) by ALC limiter operation when output level is over FS (Digital Full Scale). When output level
is not over FS, the IVL and IVR values are changed at the individual zero crossing points of Lch and Rch or at the zero
crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level
or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
MS0666-E-00
LMTH1
ALC Operation
0
0
1
1
LMAT1
0
0
1
1
ZTM1
LMTH0
0
0
1
1
0
1
0
1
LMAT0
Table 24. ALC Limiter Detection Level / Recovery Counter Reset Level
0
1
0
1
ZTM0
ALC Limier Detection Level
ALC Output ≥ − 2.5dBFS
ALC Output ≥ − 4.1dBFS
ALC Output ≥ − 6.0dBFS
ALC Output ≥ − 8.5dBFS
0
1
0
1
ALC Output
≥ LMTH
Table 26. ALC Zero Crossing Timeout Period
1024/fs
128/fs
256/fs
512/fs
1
2
2
1
Table 25. ALC Limiter ATT Step
ALC Output
128ms
8kHz
16ms
32ms
64ms
ALC Limiter ATT Step
≥ FS
- 67 -
Zero Crossing Timeout Period
1
2
4
2
(Table
ALC Recovery Waiting Counter Reset Level
− 2.5dBFS > ALC Output ≥ − 4.1dBFS
− 4.1dBFS > ALC Output ≥ − 6.0dBFS
− 6.0dBFS > ALC Output ≥ − 8.5dBFS
− 8.5dBFS > ALC Output ≥ − 12dBFS
26). IVL and IVR values are attenuated 1 step
16kHz
ALC Output
16ms
32ms
64ms
≥ FS + 6dB
8ms
1
2
4
4
44.1kHz
11.6ms
23.2ms
2.9ms
5.8ms
≥ FS + 12dB
Figure
ALC Output
1
2
8
8
60.
(default)
(Table
(default)
24), the IVL
(Table
(default)
[AK4671]
(Table
2007/10
25).
24)