mt9160bsr1 Zarlink Semiconductor, mt9160bsr1 Datasheet - Page 6

• Manufacturer Part Number: mt9160bsr1
• Description: 5v Multi-featured Phone Codec With Programmable U/a Law Companding
• Manufacturer: Zarlink Semiconductor

The serial microport, compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0,CPHA=0) and National
Semiconductor Microwire specifications provides access to all MT9160B/61B internal read and write registers. This
microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a
synchronous data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an
open-drain interrupt output (IRQ).
The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The
device then automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National
requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is
defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during
chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must
be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual
port Motorola controller configuration usually supports full-duplex communication, only half-duplex communication
is possible in the MT9160B/61B. The micro must discard non-valid data which it clocks in during a valid write
transfer to the MT9160B/61B. During a valid read transfer from the MT9160B/61B data simultaneously clocked out
by the micro is ignored by the MT9160B/61B.
All data transfers through the microport are two-byte transfers requiring the transmission of a Command/Address
byte followed by the data byte written or read from the addressed register. CS must remain asserted for the
duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT9160B/61B
that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always
used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains
information detailing whether the second byte transfer will be a read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte between the MT9160B/61B and the microcontroller. At the
end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state
the output driver of DATA1 which will remain tri-stated as long as CS is high.
3 The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
1 Delays due to internal processor timing which are transparent.
2 The MT9160:-latches received data on the rising edge of SCLK.
4 A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
5 The COMMAND/ADDRESS byte contains:
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
subsequent byte is always data until terminated via CS returning high.
2
3
D
0
D
-outputs transmit data on the falling edge of SCLK.
COMMAND/ADDRESS
1
D
2
D
3
D
4
Figure 4 - Serial Port Relative Timing for Intel Mode 0
D
5
D
6
5
D
7
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
1
D
D
Zarlink Semiconductor Inc.
0
0
MT9160B/61B
D
D
1
1
DATA INPUT/OUTPUT
D
D
2
2
D
D
6
3
3
D
D
4
4
D
D
5
5
D
D
6
6
D
X
7
D
D
7
7
4
3
X
1
D
D
0
0
X
D
D
4
1
1
COMMAND/ADDRESS:
D
D
X
2
2
D
D
3
3
A
2
D
D
4
4
D
A
D
1
5
5
D
Data Sheet
D
6
6
A
0
D
D
7
7
R/W
D
0