mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 138
mt90224
Manufacturer Part Number
mt90224
Description
8-port Ima/tc Phy Device
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90224.pdf
(155 pages)
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Note
Note 1: t
AC Electrical Characteristics - External Memory Interface Timing - Write Access
t
t
t
t
t
t
t
t
t
t
CLK
WC
AVWS
AVWH
CSWS
CSWH
WEWS
WEWH
WDS
WDH
Item
‡
: Typical figures are at 25
Note: The SR_WE signal stays LOW until a READ cycle is to be performed.
System Clock
WC
SR_A[18:0]
SR_D[7:0]
= t
Refer to SRAM Control Register to select the number of cycles.
SR_WE
SR_CS
CLK
MT90222/3/4 System Clock Period
Write Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Enable* Setup Time
Write Enable* Hold Time
Data Setup Time
Data Hold Time
- t
CSWS.
°
Figure 30 - External Memory Interface Timing - Write Cycle
C, V
Description
DD
=3.3 V, and for design aid only: not guaranteed and not subject to production testing.
Zarlink Semiconductor Inc.
MT90222/3/4
t
avws
t
t
wds
csws
138
t
wews
Address Valid
12.5 ns
Data Valid
t
19 ns
cswh
Min.
t
0 ns
0 ns
1 ns
1 ns
0 ns
0 ns
0 ns
wc
1
Typ.
20 ns
t
avwh
t
wdh
‡
t
wewh
t
clk
Data Sheet
7.5 ns
7.5 ns
9.5 ns
9.5 ns
19 ns
Max.
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