ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 245

no-image

ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
Preliminary
8.7: BCACH Line Status Register
These registers are useful only in diagnostic testing of the cache logic. Each register will contain a bit signifi-
cant flag indicating the current status of the associated cache line.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
30-12
Bit(s)
7-6
5-4
31
11
10
9
8
Valid Tag
Reserved
Loaded by PCI Read
Loaded by Predictive Fill
Loaded by RXQUE Advice
Loaded by PCI Write
Reserved
LRU bits
Function
32 bits
Read Only
Tag Number 0
Tag Number 1
Tag Number 2
Tag Number 3
Tag Number 0
Tag Number 1
Tag Number 2
Tag Number 3
None
Reserved
When set, this indicates that the associated tag register contains a valid tag.
Reserved
When set, this bit indicates that the associated tag register was loaded due to a read
request from the PCI bus
When set, this bit indicates that the associated tag register was loaded due to a predictive
fill request
When set, this bit indicates that the associated tag register was loaded due to advice from
the receive queue entity
When set, this bit indicates that the associated tag register was loaded due to a write
request from the PCI bus
Reserved
These bits indicate the cache lines current position with respect to the least recently used
algorithm. A value of ‘0’ indicates it is the most recently used while a value of ‘3’ indicates
the least recently used.
XXXX 1088
XXXX 10A8
XXXX 10C8
XXXX 10E8
X’0000 0000’
X’0000 0010’
X’0000 0020’
X’0000 0030’
Description
IBM Processor for Network Resources
The Bus DRAM Cache Controller (BCACH)
9
8
7
6
5
4
Page 245 of 676
IBM3206K0424
3
2
1
0

Related parts for ibm3206k0424