k4s1g0732d Samsung Semiconductor, Inc., k4s1g0732d Datasheet - Page 4

• Manufacturer Part Number: k4s1g0732d
• Description: St.16m X 8bit X 4 Banks Sdram
• Manufacturer: Samsung Semiconductor, Inc.

SDRAM stacked 1Gb D-die (x4, x8)
1.0 Features
2.0 General Description
3.0 Ordering Information
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• 54pin TSOP II
•
33,554,432 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle
control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory
system applications
RoHS compliant
The K4S1G0632D / K4S1G0732D is 1,073,741,824bits synchronous high data rate Dynamic RAM organized as 4 x 67,108,864/ 4 x
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8)
-. Burst type (Sequential & Interleave)
K4S1G0632D-UC75
K4S1G0732D-UC75
Part No.
Pb-Free
package
Organization
st.256Mx4
st.128Mx8
Row & Column address configuration
Orgainization
st.256Mb x4
st.128Mb x8
Row Address
A0~A12
A0~A12
Max Freq.
133MHz
133MHz
Column Address
A0-A9, A11
A0-A9, A11
Rev. 1.0 November. 2005
Interface
LVTTL
54pin TSOP(II)
Package
SDRAM