r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 78
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r8a66597
Manufacturer Part Number
r8a66597
Description
Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A66597.pdf
(185 pages)
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Part Number:
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R8A66597FP/DFP/BG
R e v 1 . 0 1
10-9 Unassigned. Fix to "0".
Bit
15
14
13
12
11
♦ DCP control register [DCPCTR]
8
7
6
5
4
3 Unassigned. Fix to "0".
2
BSTS SUREQ CSCLR CSSTS
15
0
-
BSTS
Buffer status
SUREQ
Setup token transmit
CSCLR
CSPLIT status clear of split
transaction
CSSTS
Complete split (C-SPLIT) status
of split transaction
SUREQCLR
SUREQ bit clear
SQCLR
Toggle bit clear
SQSET
Toggle bit set
SQMON
Sequence toggle bit monitor
SPBUSY
Pipe busy
PINGE
PING token issue enabled
CCPL
Control transfer end enabled
14
0
-
O c t 1 7 , 2 0 0 8
Name
13
0
-
12
0
-
p a g e 7 8 o f 1 8 3
SUREQCLR
11
0
-
Access possibility status of DCP FIFO buffer is set.
0: Buffer access is disabled
1: Buffer access is enabled
When the Host Controller function is selected, the Setup
packet is transmitted by writing "1" to this bit.
0: Invalid
1: Transmit Setup packet
When the Host Controller function is selected, regarding
the transfer using Split Transaction, the CSSTS bit can
be cleared to "0" by writing "1" to this bit. In this case, the
next DCP transfer restarts from SSPLIT.
0: Invalid
1: Clear CSSTS bit
When the Host Controller is selected, the split
transaction C-SPLIT status is set.
0: During the Start-Split (S-SPLIT) transaction process or
during the process of the device in which the split
transaction is not used
1: During the C-SPLIT transaction process
When the Host Controller is selected, the SUREQ bit can
be cleared by writing "1" to this bit.
0: Invalid
1: Clear SUREQ bit to "0"
In DCP transfer, the expected value of sequence toggle
bit of next transaction can be written to DATA0.
0: Invalid
1: Specifies DATA0
In the DCP transfer, the expected value of the sequence
toggle bit of the next transaction can be written to
DATA1.
0: Invalid
1: Specifies DATA1
In the DCP transfer, the expected value of the sequence
toggle bit of the next transaction is set.
0: DATA0
1: DATA1
When the PID bit of the DCP is modified from BUF to
0: Transition to NAK is incomplete
1: Transition to NAK is complete
When the Host Controller function is selected, the PING
token can be used in an OUT transaction by writing "1"
to this bit.
0: PING token issue disabled
1: Normal PING operation
When the Peripheral Controller function is selected,
status stage end of control transfer is enabled by writing
"1" to this bit.
0: Invalid
1: Control transfer end enabled
NAK, it is written to whether the actual communication of
the DCP is transited to NAK status or not.
10
?
?
9
?
?
SQCLR SQSET
8
0
-
Function
7
0
-
SQMON
6
1
-
PBUSY PINGE
5
0
-
4
0
-
R(0)/W(1)
R(0)/W(1)
R(0)/W(1)
R(0)/W(1)
R(0)/W(1)
Software Hardware Remarks
R/W(1)
R/W
3
?
?
R
R
R
R
CCPL
2
0
0
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W
W
W
W
<Address: 60H>
R
R
R
1
0
0
PID
"0" when
"0" when
"0" when
"0" when
"0" when
(Write to
(Write to
(Write to
(Write to
(Write to
when P)
(Invalid
value
read
P")
P")
P")
P")
P)
H
H
H
H
H
P
0
0
0