as4c8m16s Alliance Memory, Inc, as4c8m16s Datasheet - Page 19

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as4c8m16s

Manufacturer Part Number
as4c8m16s
Description
128mb/ 8m X 16 Bit Synchronous Dram Sdram
Manufacturer
Alliance Memory, Inc
Datasheet

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Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
(V
* CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
2. All voltages are referenced to V
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
RCD
RP
RRD
RAS
WR
CCD
CK
CH
CL
AC
OH
LZ
HZ
IS
IH
PDE
REFI
XSR
DD
the device.
width ≤ 3ns.
minimum value of t
FEBRUARY 2011
= 3.3V ± 0.3V, T
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate
command (same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time
CAS# to CAS# Delay time
Clock cycle time
Clock high time
Clock low time
Access time from CLK
(positive edge)
Data output hold time
Data output low impedance
Data output high impedance
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Power Down Exit set-up time
Refresh Interval Time
Exit Self Refresh to Read Command time
A
= 0~70°C) (Note: 5, 6, 7, 8)
CK
A.C. Parameter
and t
RC
. Input signals are changed one time during every 2 t
SS
. VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.5V for pulse
CL* = 2
CL* = 3
CL* = 2
CL* = 3
t
t
IS+
IS+
Min
2.5
2.5
2.5
1.5
60
18
18
12
42
19
2
1
9
6
1
1
-
-
-
-
t
t
CK
RC
-6
Max.
100k
15.6
6
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
t
IS+
IS+
Min
2.5
2.5
2.7
1.5
63
21
21
14
42
10
2
1
7
1
1
-
-
-
-
t
t
CK
RC
-7
CK
.
100k
Max.
15.6
5.4
5.4
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AS4C8M16S
Unit Note
t
ns
ns
µs
ns
CK
10
10
10
10
10
9
9
8

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