as4c8m16s Alliance Memory, Inc, as4c8m16s Datasheet - Page 7

• Manufacturer Part Number: as4c8m16s
• Description: 128mb/ 8m X 16 Bit Synchronous Dram Sdram
• Manufacturer: Alliance Memory, Inc

FEBRUARY 2011
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
t
t
t
CK2,
CAS# latency=2
CAS# latency=3
CLK
COMMAND
t
CK2,
CK3,
CLK
COMMAND
CAS# latency=2
CAS# latency=3
CK3,
Figure 5. Read Interrupted by a Read
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
DQ
DQ
DQ
DQ
Figure 4. Burst Read Operation
T0
READ A
READ A READ B
T0
T1
NOP
T1
DOUT A
T2
NOP
DOUT A
T2
NOP
0
0
DOUT A
DOUT A
T3
DOUT A
NOP
DOUT B
T3
NOP
(Burst Length = 4, CAS# Latency = 2, 3)
1
0
(Burst Length = 4, CAS# Latency = 2, 3)
0
DOUT A
DOUT A
0
T4
7
DOUT B
DOUT B
NOP
T4
NOP
2
1
1
0
DOUT A
DOUT A
T5
DOUT B
DOUT B
T5
NOP
NOP
3
2
2
1
DOUT A
T6
DOUT B
DOUT B
T6
NOP
NOP
3
3
2
DOUT B
T7
T7
NOP
NOP
3
AS4C8M16S
T8
NOP
T8
NOP