gvt71128e36 ETC-unknow, gvt71128e36 Datasheet - Page 3

• Manufacturer Part Number: gvt71128e36
• Description: 128k Synchronous Burst Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS
February 27, 1997
Rev. 2/97
GALVANTECH
37, 36, 35, 34, 33,
32, 100, 99, 82, 81,
44, 45, 46, 47, 48,
49,50
TQFP PINS
93,94,95,96
87
88
89
98
92
SYMBOL
A0-A16
BW1#,
BW2#,
BW3#,
BWE#
BW4#
CE2#
GW#
CLK
CE#
VCCQ
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
VSSQ
DQP3
DQP4
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
VCC
VSS
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
NC
NC
TYPE
Input-
Input-
Input-
Input-
Input-
Input-
Input-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
, INC.
100 99
31
32
98
33
PIN ASSIGNMENT (Top View)
Addresses: These inputs are registered and must meet the setup and hold times around
the rising edge of CLK. The burst counter generates internal addresses associated with A0
and A1, during burst cycle and wait cycle.
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW1#
controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and DQP2. BW3# controls
DQ17-DQ24 and DQP3. BW4# controls DQ25-DQ32 and DQP4. Data I/O are high
impedance if either of these inputs are LOW, conditioned by BWE# being LOW.
Write Enable: This active LOW input gates byte write operations and must meet the setup
and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur independent of the
BWE# and BWn# lines and must meet the setup and hold times around the rising edge of
CLK.
Clock: This signal registers the addresses, data, chip enables, write control and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to gate ADSP#.
Chip Enable: This active LOW input is used to enable the device.
97
34
96
35
95
36
94
37
100-pin PQFP
100-pin TQFP
93
38
128K X 36 SYNCHRONOUS BURST SRAM
92
39
91
40
or
90
41
3
89
42
88
43
87
44
86
45
85
46
84
47
83
48
82
49
DESCRIPTION
81
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Galvantech, Inc. reserves the right to change products or specifications without notice.
DQP2
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
DQP1
GVT71128E36