ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 33

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ax500-1cs896i

Manufacturer Part Number
ax500-1cs896i
Description
Axcelerator Family Fpgas
Manufacturer
Actel Corporation
Datasheet
I/O Standard Electrical Specifications
Table 2-18 • Input Capacitance
Figure 2-9 • Input Buffer Delays
Figure 2-10 • Output Buffer Delays
Symbol
C
C
ln
Out
V
IN
INCLK
OL
(t
50%
t
DLH
PY
Input Capacitance
Input Capacitance on Clock Pin
)
V
CCA
V
50%
trip
V
OH
(t
Parameter
t
DHL
PY
)
GND
V
trip
ln
ln
Y
GND
En
En
Out
PAD
TRIBUF
(Rising)
V
V
t
trip
CCI
ENLZ
50%
t
Input High
DP
/V
TT
V
IN
OUT Pad
CCA
50%
V
50%
trip
V
V
v2.6
CCA
OL
INBUF
t
(Falling)
ENLZ
V
V
V
trip
t
IN
IN
Conditions
DP
=0, f=1.0 MHz
=0, f=1.0 MHz
To AC test loads (shown below)
GND
10%
Y
0V
50%
V
TT
En
Out
GND/V
TT
t
ENHZ
50%
V
CCA
Axcelerator Family FPGAs
Min.
50%
V
V
OH
trip
Max.
t
10
10
ENHZ
GND
90%
Units
pF
pF
V
2-19
TT

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