mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 67

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

ECSE — External Clock Synchronization Enable
This configuration flag enables/disables the External Clock Synchronization. It can be written during the
configuration state only.
1 – External Clock Synchronization is enabled.
0 – External Clock Synchronization is disabled.
CSI — Coldstart Inhibit Mode
The node can be prevented from initializing the TDMA communication schedule by setting the CSI bit to
‘1’ in the configuration state. It can be written during the configuration state only.
1 – Node is in Coldstart Inhibit mode.
0 – Node is not in Coldstart Inhibit mode.
ARL — Allow Red Level
If this bit is set, the transition to the red error handling level (Diagnosis Stop state) due to clock sync errors
is allowed. It may be written in the configuration state only.
1 – Error handling level red is allowed (the CC enters the Diagnosis Stop state).
0 – Error handling level red is prohibited (the CC enters the configuration state).
AYTG — Allow Yellow to Green
If this bit is set, the transition from the yellow error handling level to the green error handling level is
allowed. It may be written in the configuration state only.
1 – Transition from yellow to green is allowed.
0 – Transition from yellow to green is prohibited.
3.2.3.2.3
Address 0x9A
Reset
This register controls the drive strength of the MFR4200 pins identified in
Freescale Semiconductor
Reserved
Reserved
15
7
r
r
0x0
Host Interface and Physical Layer Pins Drive Strength Register (HIPDSR)
Reserved
Reserved
14
6
r
r
Figure 3-7. Host Interface Pins Drive Strength Register
Reserved
INT_CC#
13
rw
5
r
MFR4200 Data Sheet, Rev. 0
Reserved
CLKOUT
12
rw
4
r
ARM/DBG1/
Reserved
CLK_S0
11
rw
3
r
MT/CLK_S1
Reserved
10
rw
2
r
Figure
BGT/DBG2/
3-7.
Reserved
IF_SEL0
Memory Map and Registers
rw
9
1
r
PAD[0:15]/
Reserved
D[15:0]
rw
8
0
r
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