MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 53

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

2.6.4.4 Hardware Reset Configuration
Hardware reset configuration is enabled if
RSTCONF
RSTCONF
RSTCONF
2.6.4.4, Hardware Reset Configuration, explains the configuration sequence and the terms “configuration master”
and “configuration slave.”
Directly after the deassertion of
configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts
throughout the power-on reset process, including configuration. Configuration takes 1024
which
Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to
to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the
clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled.
If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is
locked. During PLL and DLL locking,
BUS clocks and is then released. The
configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time.
Figure 2-8 shows the power-on reset flow.
Freescale Semiconductor
MODCK[1–3]
Output (I/O)
PORESET
PORESET
Output (I/O)
while
is deasserted (driven high) while
is asserted (driven low) while
HRESET
SRESET
Internal
Input
PORESET
are sampled to determine the MSC8103’s working mode.
asserted for
CLKIN.
min 16
1
changes from assertion to deassertion determines the MSC8103 configuration. If
Figure 2-8.
PORESET
In reset configuration mode:
reset configuration sequence
occurs in this period.
MSC8103 Network Digital Signal Processor, Rev. 11
RSTCONF is sampled for
master/slave determination
SRESET
HRESET
PORESET
2
HPE
and choice of the reset operation mode as configuration master or
PORESET
Hardware Reset Configuration Timing
is released three bus clocks later. If the DLLDIS bit in the reset
is sampled low at the rising edge of
and
changes, the MSC8103 acts as a configuration master. Section
SRESET
changes, the MSC8103 acts as a configuration slave. If
PLL locked
800 SPLLMFCLKs. DLL
locks 3073 bus clocks after
PLL is locked.
When DLL is disabled, reset
period is shortened by 3073
bus clocks.
PLL locks after
MODCK[1–3] are sampled.
MODCK_H bits are ready
for PLL.
are asserted.
3
DLL locked
4
HRESET
MODCK[1–3]
HRESET/SRESET are
extended for 512/515 bus
clocks, respectively, from PLL
and DLL Lock time.
remains asserted for another 512
PORESET
5
6
, which are sampled, and
HRESET
CLOCKIN
. The value driven on
and
cycles, after
SRESET
AC Timings
2-13