IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 25

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2. t
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
6. First data word latency = t
Q
D
t
t
0
SKEW1
SKEW1
SKEW2
SKEW2
0
WCLK
RCLK
- Q
WEN
- D
REN
PAE
PAF
OR
HF
, then OR assertion may be delayed one extra RCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus t
IR
17
17
t
DS
t
ENS
DATA IN OUTPUT REGISTER
W
1
SKEW1
t
DH
t
SKEW1
+ 2*T
1
W
2
(1)
RCLK
+ t
2
W
REF.
3
3
W
t
t
REF
4
A
t
DS
W
[n +2]
Figure 9. Write Timing (First Word Fall Through Mode)
t
W
SKEW2
1
[n+3]
t
PAES
(2)
W
2
[n+4]
W
[
D-1
]
t
DS
W
[
D-1
]
t
HF
W
[
D-1
]
W
W
PAES
REF
[D-m-2]
1
. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
t
DS
W
[D-m-1]
W
[D-m]
1
W
[D-m+1]
t
PAFS
W
[D-m+2]
W
[D-1]
W
D
t
WFF
4667 drw 14
t
ENH