lxt972a Intel Corporation, lxt972a Datasheet - Page 19

• Manufacturer Part Number: lxt972a
• Description: 3.3v Dual-speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Intel Corporation

3.2.3.2
3.2.3.3
Datasheet
(Write)
MDIO
MDC
MDIO
(Read)
MDC
Figure 3. Management Interface Read Frame Structure
Figure 4. Management Interface Write Frame Structure
High Z
Idle
Preamble
32 "1"s
Preamble
32 "1"s
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in
page
MII Interrupts
The LXT972A provides a single interrupt pin (MDINT). Interrupt logic is shown in
LXT972A also provides two dedicated interrupt registers. Register 18 provides interrupt enable
and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables the
device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change
on the LXT972A. Interrupts may be caused by four conditions:
Hardware Control Interface
The LXT972A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.
Refer to
•
•
•
•
0
0
Auto-negotiation complete
Speed status change
Duplex status change
Link status change
53.
ST
ST
1
Section 3.4.5, “Hardware Configuration Settings” on page 23
1
Figure 3
0
1
Op Code
Op Code
and
1
0
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
Figure 4
Write
A4
A4
PHY Address
PHY Address
A3
A3
(read and write). MDIO Interface timing is shown in
A0
A0
Write
R4
R4
Register Address
Register Address
R3
R3
R0
R0
Z
Around
1
Turn
Around
Turn
0
0
D15
D15
D15
D14
for additional details.
Data
Read
D14
D14
D1
Data
D1
D1
D0
D0
Figure
Table 32 on
Idle
5. The
Idle
19