lxt972a Intel Corporation, lxt972a Datasheet - Page 26

• Manufacturer Part Number: lxt972a
• Description: 3.3v Dual-speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Intel Corporation

LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
26
The LXT972A supplies both clock signals as well as separate outputs for carrier sense and
collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
MII Clocks
The LXT972A is the master clock source for data transmission and supplies both MII clocks
(RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When
the link is operating at 100Mbps, the clocks are set to 25 MHz. When the link is operating at
10Mbps, the clocks are set to 2.5 MHz.
mode. The transmit data and control signals must always be synchronized to TX_CLK by the
MAC. The LXT972A samples these signals on the rising edge of TX_CLK.
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT972A asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
Carrier Sense
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in half-duplex when a packet is transmitted.
Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
Error Signals
When LXT972A is in 100Mbps mode and receives an invalid symbol from the network, it asserts
RX_ER and drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT972A drives “H” symbols out on the TPOP/N pins.
Collision
The LXT972A asserts its collision signal, asynchronously to any clock, whenever the line state is
half-duplex and the transmitter and receiver are active at the same time.
conditions for assertion of carrier sense, collision, and data loopback signals.
•
•
For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the
data packet.
For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
Figure 9
through
Figure 11
show the clock cycles for each
Table 9
summarizes the
Table 9
Datasheet