SST49LF020A-33-4C-NHE SST [Silicon Storage Technology, Inc], SST49LF020A-33-4C-NHE Datasheet
SST49LF020A-33-4C-NHE
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SST49LF020A-33-4C-NHE Summary of contents
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... Erase and Program time increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST49LF020A device is offered in 32-lead TSOP and 32- lead PLCC packages. See Figures 2 and 3 for pin assign- ments and Table 1 for pin descriptions. ...
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... Silicon Storage Technology, Inc. 2 Mbit LPC Flash 2 SST49LF020A S71206-08-000 5/06 ...
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... Data Protection (PP Mode Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Software Data Protection (SDP SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PRODUCT ORDERING INFORMATION Valid combinations for SST49LF020A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ©2006 Silicon Storage Technology, Inc. 3 Data Sheet S71206-08-000 5/06 ...
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... FIGURE 37: Erase Command Sequence Flowchart (PP Mode FIGURE 38: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code FIGURE 39: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code ©2006 Silicon Storage Technology, Inc. 2 Mbit LPC Flash 4 SST49LF020A S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A LIST OF TABLES TABLE 1: Pin Description TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3: Address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 4: Address Decoding Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 5: LPC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 6: LPC Write Cycle TABLE 7: Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 8: General Purpose Inputs Register TABLE 9: Memory Map Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 10: Operation Modes Selection (PP Mode) ...
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... LCLK LPC LFRAME# Interface ID[3:0] GPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic MODE RST# CE Mbit LPC Flash SST49LF020A SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1206 B1.1 S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A PIN ASSIGNMENTS A6 (GPI0) A5 (WP#) A4 (TBL#) DQ0 (LAD0) FIGURE 2: Pin Assignments for 32-lead PLCC (CE#) 4 MODE (MODE) 5 A10 (GPI4) 6 R/C# (LCLK RST# (RST (GPI3 (GPI2 (GPI1 (GPI0 (WP#) ...
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... This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode Unconnected pins Mbit LPC Flash SST49LF020A ) for PP mode and low (V ) for LPC mode T1.0 1206 S71206-08-000 ...
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... Mbit LPC Flash SST49LF020A DEVICE MEMORY MAPS TBL# WP# for Block 0~14 FIGURE 4: Device Memory Map ©2006 Silicon Storage Technology, Inc. 3FFFFH Block 15 Boot Block 3C000H 3BFFFH Block 14 38000H 37FFFH Block 13 34000H 33FFFH Block 12 30000H 2FFFFH Block 11 2C000H 2BFFFH Block 10 28000H 27FFFH Block 9 ...
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... CE# must be asserted one cycle before the start cycle to select the SST49LF020A for Read and Write operations. Once the SST49LF020A identify the operation as valid (a start value of all zeros), it next expects a nibble that indi- cates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address cycles ...
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... The CE# pin, enables and disables the SST49LF020A, controlling read and write access of the device. To enable the SST49LF020A, the CE# pin must be driven low one clock cycle prior to LFRAME# being driven low. The device will enter standby mode when internal Write operations are completed and CE# is high ...
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... This field is the least-significant nibble of the data byte. OUT This field is the most-significant nibble of the data byte. OUT In this clock cycle, the SST49LF020A has driven the bus to all then Float 1s and then floats the bus. This is the first part of the bus “turn- around cycle.” ...
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... IN then Float In this clock cycle, the host has driven the bus to all ‘1’s and then floats the bus. This is the first part of the bus “turnaround cycle.” Float then OUT The SST49LF020A takes control of the bus during this cycle. 0000 OUT The SST49LF020A outputs the values 0000, indicat- ing that it has received data or a flash command ...
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... If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling When the SST49LF020A device is in the internal Program operation, any attempt to read D[7] will produce the com- plement of the true data. Once the Program operation is completed, D[7] will produce true data ...
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... IDs. See 21 18 Table 7 for IDs. The SST49LF020A will compare these bits with ID[3:0]’s strapping values. If there is a mismatch, the device will ignore the reminder of the cycle. TABLE 7: Multiple Device Selection Configuration Hardware ...
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... General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF020A recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle ...
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... SST49LF020A. See Table 23 for Reset timing parameters and Figure 17 for Reset timing diagram. Read The Read operation of the SST49LF020A device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 18, for further details. ...
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... If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid. Data# Polling ( When the SST49LF020A device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data. Once the Program operation is completed, DQ will produce true data ...
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... Silicon Storage Technology, Inc. Software Data Protection (SDP) The SST49LF020A provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three- ...
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... Sector-Erase Address for Block-Erase Address X 6. Chip-Erase is supported in PP mode only 7. SST Manufacturer’ BFH, is read with A With SST49LF020A Device ID = 52H, is read with Both Software ID Exit operations are equivalent ©2006 Silicon Storage Technology, Inc 2nd 3rd ...
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... Mbit LPC Flash SST49LF020A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# 3rd Start LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write ...
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... Read the see if internal write complete or not. Address 1 TAR A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State Load Address in 8 Clocks 2 Clocks When internal write complete, the DQ 7 will equal to D7 Mbit LPC Flash SST49LF020A Start next Data TAR Sync Command 0000b TAR Dn[7:4] 1111b Tri-State 0000b 1 Clock 2 Clocks 1 Clock ...
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... Mbit LPC Flash SST49LF020A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock Note: 1. Address must be within memory address range specified in Table 4. ...
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... A[23:20] A[19:16] Load Sector Address in 8 Clocks Load Data “30” Clocks Write the 6th command (target sector to be erased) to the device in LPC mode Sector Address 24 2 Mbit LPC Flash SST49LF020A Start next Command Data TAR Sync TAR 1010b 1111b ...
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... Mbit LPC Flash SST49LF020A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle 0000b 011Xb LAD[3:0] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CE# ...
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... Clock 1 Clock Note: 1. See Table 9 for register addresses. FIGURE 12: Register Readout Command Sequence (LPC Mode) ©2006 Silicon Storage Technology, Inc. Address 1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks 26 2 Mbit LPC Flash SST49LF020A Start next TAR Sync Data 0000b TAR 1111b Tri-State 0000b D[3:0] D[7:4] 1 Clock 2 Clocks ...
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... Mbit LPC Flash SST49LF020A ELECTRICAL SPECIFICATIONS The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 12 for the DC voltage and current speci- fications. Refer to Tables 16 through 19 and Tables 21 through 23 for the AC timing specifications for Clock, Read, Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “ ...
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... I =1500 µ 0 =-500 µ LFRAME# = IH, RC min =3.3V, Ta=25 °C, f=1 Mhz, other pins open Mbit LPC Flash SST49LF020A and Address Input (PP mode) (PP Mode) TRC min Max and Address Input (PP mode) (PP Mode) TRC min , f=33 MHz, CE#=0.9 V ...
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... Mbit LPC Flash SST49LF020A TABLE 15: Reliability Characteristics Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 16: Clock Timing Parameters (LPC Mode) ...
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... Silicon Storage Technology, Inc. =3.0-3.6V (LPC Mode reset procedure is performed during a Program or Erase operation. RSTE T PRST T KRST T RSTP T RSTF =3.0-3.6V (LPC Mode Mbit LPC Flash SST49LF020A Min Max Units 1 ms 100 µs 100 µs 10 µs T17.0 1206 Sector-/Block-Erase ...
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... Mbit LPC Flash SST49LF020A TABLE 19: AC Input/Output Specifications (LPC Mode) Symbol Parameter I (AC) Switching Current High OH (Test Point) I (AC) Switching Current Low OL (Test Point) I Low Clamp Current CL I High Clamp Current CH 2 slewr Output Rise Slew Rate 2 slewf Output Fall Slew Rate 1 ...
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... Silicon Storage Technology, Inc. V TEST T SU Inputs Valid Value overdrive over V and V . Timing parameters must be met with no more over Mbit LPC Flash SST49LF020A MAX 1206 F17.0 Units V/ns T20.0 1206 S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A TABLE 21: Read Cycle Timing Parameters, V Symbol Parameter T Read Cycle Time RC T RST# High to Row Address Setup RST T R/C# Address Set-up Time AS T R/C# Address Hold Time AH T Address Access Time AA T Output Enable Access Time OE T OE# Low to Active Output ...
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... T PRST T RSTF T RST T RC Row Address Column Address OLZ 34 2 Mbit LPC Flash SST49LF020A Row Address T RSTP Sector-/Block-Erase T RSTE or Program operation aborted T RSTC Chip-Erase aborted T RST 1206 F18.0 Row Address Column Address OHZ ...
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... Mbit LPC Flash SST49LF020A T RST RST# Row Address Addresses T AS R/C# OE# WE# DQ 7-0 FIGURE 19: Write Cycle Timing Diagram (PP Mode) Row Addresses R/C# WE# OE FIGURE 20: Data# Polling Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. Column Address CWH OEH T OES ...
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... FIGURE 21: Toggle Bit Timing Diagram (PP Mode) A 14-0 (Internal A ) 5555 MS-0 R/C# OE# WE Byte-Program Address A = Most Significant Address MS FIGURE 22: Byte-Program Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. T OET 2AAA 5555 Mbit LPC Flash SST49LF020A D 1206 F22.0 BA Internal Program Starts DATA 1206 F23.0 S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A A 14-0 (Internal A ) 5555 MS-0 R/C# OE Sector Address X FIGURE 23: Sector-Erase Timing Diagram (PP Mode) A 14-0 (Internal A ) 5555 MS-0 R/C# OE Block Address X FIGURE 24: Block-Erase Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. 2AAA 5555 5555 2AAA 5555 5555 Data Sheet ...
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... OE# WE 7-0 FIGURE 25: Chip-Erase Timing Diagram (PP Mode) A 14-0 (Internal A ) 5555 MS-0 R/ 7-0 Note: Device ID = 52H for SST49LF020A FIGURE 26: Software ID Entry and Read (PP Mode) A 14-0 (Internal A ) MS-0 R/C# OE# WE# DQ 7-0 FIGURE 27: Software ID Exit (PP Mode) ©2006 Silicon Storage Technology, Inc. 2AAA 5555 5555 55 80 2AAA 5555 ...
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... Mbit LPC Flash SST49LF020A V IHT INPUT V ILT AC test inputs are driven at V (0.9 V IHT points for inputs and outputs are V FIGURE 28: AC Input/Output Reference Waveforms TO DUT FIGURE 29: A Test Load Example ©2006 Silicon Storage Technology, Inc REFERENCE POINTS ) for a logic “1” and V (0 ...
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... Mbit LPC Flash Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address: A Write Data: D Cycle: 4 Wait T BP Available for Next Byte 1206 F32.0 FIGURE 31: Byte-Program Flowchart (LPC Mode) 40 SST49LF020A IN IN S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A Command Sequence Address: 2AAAH Address: 2AAAH FIGURE 32: Erase Command Sequences Flowchart (LPC Mode) ©2006 Silicon Storage Technology, Inc. Block-Erase Sector-Erase Command Sequence Address: 5555H Address: 5555H Write Data: AAH Write Data: AAH Cycle: 1 Cycle: 1 Address: 2AAAH Write Data: 55H ...
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... Address: 5555H Write Data: F0H Cycle: 3 Wait T IDA Available for Next Command Note: X can but no other value Mbit LPC Flash SST49LF020A Address: XXXXH Write Data: F0H Cycle: 1 Wait T IDA Available for Next Command 1206 F34.0 S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A FIGURE 34: Byte-Program Command Sequences Flowchart (PP Mode) ©2006 Silicon Storage Technology, Inc. Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling ...
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... Silicon Storage Technology, Inc. Toggle Bit Byte- Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed 44 2 Mbit LPC Flash SST49LF020A Data# Polling Byte- Program/Erase Initiated Read true data? Yes Program/Erase Completed 1206 F36.0 S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A Software Product ID Entry Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 36: Software Product ID Command Sequences Flowchart (PP Mode) ©2006 Silicon Storage Technology, Inc. Software Product ID Exit ...
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... Address: 5555H Address: 5555H Write data: 55H Write data: 55H Address: 2AAAH Address: 2AAAH Write data: 50H Write data: 30H Address: BA Address Wait T Wait T BE Block erased Sector erased to FFH 46 2 Mbit LPC Flash SST49LF020A FFH 1206 F38.0 S71206-08-000 5/06 ...
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... SST49LF0x0A - XXX - XX Valid combinations for SST49LF020A SST49LF020A-33-4C-WHE SST49LF020A-33-4C-NHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. ...
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... Silicon Storage Technology, Inc. SIDE VIEW .112 .106 .029 .020 R. .040 x 30˚ R. .023 .030 MAX. .021 .013 .400 .032 BSC .026 .050 BSC .015 Min. .095 .075 .140 .125 48 2 Mbit LPC Flash SST49LF020A BOTTOM VIEW .530 .490 .032 .026 32-plcc-NH-3 S71206-08-000 5/06 ...
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... Mbit LPC Flash SST49LF020A Pin # 1 Identifier 12.50 12.30 0.70 0.50 14.20 13.80 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. FIGURE 39: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH © ...
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... TABLE 24: Revision History Number 00 • Initial release 01 • Added SST49LF030A to the data sheet 02 • Added SST49LF020A to the data sheet 03 • Corrected LFRAME and CE# test conditions for Standby V 04 • Removed SST49LF040A from the data sheet • Added support for bottom address space to SST49LF030A 05 • ...