x24042 ETC-unknow, x24042 Datasheet - Page 7

• Manufacturer Part Number: x24042
• Description: Serial E2prom
• Manufacturer: ETC-unknow

X24042
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Current Address Read
Internally the X24042 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
a read or write) was to address n, the next read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W set to one, the X24042
issues an acknowledge and transmits the eight bit word.
Figure 7. Current Address Read
Figure 8. Random Read
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24042
R
S
T
A
T
S
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24042
ADDRESS
SLAVE
C
A
K
S
A
R
S
T
T
ADDRESS n
ADDRESS
WORD
SLAVE
7
The read operation is terminated by the master; by not
responding with an acknowledge and by issuing a stop
condition. Refer to Figure 7 for the sequence of address,
acknowledge and data transfer.
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition, and the slave address
followed by the word address it is to read. After the word
address acknowledge, the master immediately reissues
the start condition and the slave address with the R/W bit
set to one. This will be followed by an acknowledge from
the X24042 and then by the eight bit word. The read
operation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
Refer to Figure 8 for the address, acknowledge and data
transfer sequence.
A
C
K
C
A
K
R
S
T
A
T
S
ADDRESS
DATA
SLAVE
A
C
K
O
S
T
P
P
DATA n
O
S
T
P
P
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