w89c940 Winbond Electronics Corp America, w89c940 Datasheet - Page 47
w89c940
Manufacturer Part Number
w89c940
Description
Elanc-pci Twisted-pair Ether-lan Controller With Pci Interface
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W89C940.pdf
(61 pages)
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Remote Read Word Access Cycle
CLK
Note:
FRAME#
AD[31::0]
C_BE#[3:0]
TRDY#
DEVSEL#
MSD0-7
IRDY#
MSRDB
RCSB
MSWRB
MSA0-13
(Read)
T2
T3
T4
T5
T6
T7
T1
T2
T3
T4
T5
1) The other timing requirements for PCI signal are as the read transaction timing.
2) n=0,1,2,3,..... when local DMA get the control of the bus, PCI bus will insert wait state.
Wait state number is n.
clock n+6 to MSA valid
clock n+7 to RCSB deasserted time
clock n+4 to MSRDB valid
clock n+7 to MSRDB deasserted time
MSD setup tim to clock n+6
MSD hold time from clock n+6
clock n+4 to RCSB and MSA valid (note
2)
clock n+6 to MSA valid
clock n+7 to RCSB deasserted time
clock n+4 to MSRDB valid
clock n+7 to MSRDB deasserted time
0
ADDRESS
BUS CMD
1
2
3
n+4
T1
T4
n+5
T6
n+6
T2
T7
47
BE#'s
T6
10
15
10
15
25
22
20
25
22
7
0
n+8
T8
T7
n+9
T3
T5
DATA
n+10
28
15
27
20
25
28
15
27
20
n+11
25
25
30
30
30
30
30
W89C940
20
20
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
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