cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 210

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

Table 13-3. FCLK PLL Generated Clocks
Table 13-4. BCLK PLL Generated Clocks
Table 13-5. FCLK PLL Generated Clocks Programming Examples
Table 13-6. BCLK PLL Generated Clocks Programming Examples
13-4
FCLK
UCLK
UDC
BCLK
PCLK
EPCLK
(PLL_F_CR_SLOW)
BCLK Speed Select
(PLL_F_CR_SLOW)
FCLK Speed Select
Clock
Clock
0 (Normal)
0 (Normal)
0 (Normal)
0 (Normal)
0 (Normal)
0 (Normal)
1 (Slow)
1 (Slow)
1 (Slow)
1 (Slow)
1 (Slow)
1 (Slow)
Frequency
Frequency
Minimum
Minimum
(MHz)
(MHz)
12.5
96
48
12
25
25
Frequency
Frequency
Conexant Proprietary and Confidential Information
120 MHz
144 MHz
168 MHz
120 MHz
144 MHz
168 MHz
100 MHz
100 MHz
Frequency
Frequency
96 MHz
96 MHz
75 MHz
50 MHz
PLL_B
Operating
Operating
PLL_F
Maximum
Maximum
(MHz)
(MHz)
168
100
84
12
50
25
CX82100 Home Network Processor Data Sheet
FCLK (ARM)
BCLK (ASB)
ARM940T fast clock input, asynchronous to bus clock. Can have a lower minimum if
the USB interface is not used. Internal. FCLK must be equal to or greater than BCLK.
USB timing reference; always one-half the frequency of FCLK. Must be a multiple of
12 MHz for proper USB operation. Internal. Optionally external, output on FCLKIO
pin.
USB timing reference. Must be 12 MHz for proper USB operation; UCLK divided by
number corresponding to PLL_F_CR. Internal.
ASB clock. Internal. Can have a lower minimum if EPCLK is not used for 25 MHz.
APB clock; always one-half the frequency of BCLK and aligned to BCLK falling edge.
Internal.
Miscellaneous timing reference, e.g., Ethernet PHY. Optionally external; output on
BCLKIO pin. Can be different frequency for applications other than an Ethernet PHY
clock.
Frequency
Frequency
120 MHz
144 MHz
168 MHz
100 MHz
96 MHz
48 MHz
60 MHz
72 MHz
84 MHz
75 MHz
25 MHz
50 MHz
PCLK (APB)
Frequency
Frequency
(BCLK/2)
37.5 MHz
(FCLK/2)
12.5MHz
48 MHz
60 MHz
72 MHz
84 MHz
48 MHz
60 MHz
72 MHz
84 MHz
50 MHz
25 MHz
UCLK
EPCLK Clock
(PLL_B_CR)
(PLL_F_CR)
Description
Description
Rate Select
Rate Select
USB Clock
01 ( ÷ 10)
10 ( ÷ 12)
10 ( ÷ 14)
00 ( ÷ 8)
00 ( ÷ 4)
01 ( ÷ 5)
10 ( ÷ 6)
10 ( ÷ 7)
00 ( ÷ 3)
01 ( ÷ 4)
00 ( ÷ 1)
01 ( ÷ 2)
UDC Clock
Frequency
Frequency
(XBCLK)
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
EPCLK
25 MHz
25 MHz
25 MHz
25 MHz
Clock
Default at POR
Default at POR
Notes
Notes
101306C