alc885-gr Realtek Semiconductor Corporation, alc885-gr Datasheet - Page 26

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alc885-gr

Manufacturer Part Number
alc885-gr
Description
7.1+2 Channel High-performance Hda Codec With Content Protection
Manufacturer
Realtek Semiconductor Corporation
Datasheet

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7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
An initialization sequence is requested after any of the following three events:
1.
2.
3.
7.3.1.
A link reset may be caused by 3 events:
1.
2.
3.
Enter ‘Link Reset’:
7.1+2 Channel High-Performance HDA Codec
With Content Protection
Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
All link signals driven by controller and codecs should be tri-state by internal pull low resistors
link reset
the end of the frame
state
Link Reset
Codec Reset
Codec changes its power state (for example, hot docking a codec to an HDA system)
The HDA controller asserts RST# for any reason (power up, or PCI reset)
Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
Software initiates power management sequences. Figure 13, page 19, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence ( ~ ) and ‘Exit’ sequence ( ~ )
Link Reset
18
ALC885 Series
Datasheet
Rev. 1.1