alc885-gr Realtek Semiconductor Corporation, alc885-gr Datasheet - Page 27

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alc885-gr

Manufacturer Part Number
alc885-gr
Description
7.1+2 Channel High-performance Hda Codec With Content Protection
Manufacturer
Realtek Semiconductor Corporation
Datasheet

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Exit from ‘Link Reset’:
7.3.2.
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
7.1+2 Channel High-Performance HDA Codec
With Content Protection
SYNC
BCLK
SDOs
RST#
SDIs
If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
100µsec provides time for the codec PLL to stabilize)
last bit of frame SYNC, it means the codec requests an initialization sequence)
Codec Reset
1
2
SYNC is absent
Previous Frame
Normal Frame
3
Driven Low
Driven Low
Driven Low
4 BCLK
Figure 13. Link Reset Timing
4
4 BCLK
19
5
Pulled Low
Pulled Low
Pulled Low
Pulled Low
Link in Reset
6
>=100 usec
7
>= 4 BCLK
Wake Event
8
ALC885 Series
Initialization Sequence
Normal Frame
SYNC
Datasheet
9
Rev. 1.1