alc885-gr Realtek Semiconductor Corporation, alc885-gr Datasheet - Page 8

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alc885-gr

Manufacturer Part Number
alc885-gr
Description
7.1+2 Channel High-performance Hda Codec With Content Protection
Manufacturer
Realtek Semiconductor Corporation
Datasheet

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Part Number
Manufacturer
Quantity
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Company:
Part Number:
ALC885-GR
Manufacturer:
REALTEK/
Quantity:
6 000
Table 90. Link Reset and Initialization Timing ........................................................................................79
Table 91. Link Timing Parameters at the Codec.......................................................................................80
Table 92. S/PDIF Output and Input Timing..............................................................................................81
Table 93. Analog Performance .................................................................................................................82
Table 94. Standby Mode ...........................................................................................................................86
Table 95. Volume Code Corresponding to DC Level at Pin 33................................................................87
Table 96. Ordering Information ................................................................................................................90
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. SDI Inbound Stream................................................................................................................14
Figure 11. SDI Stream Tag and Data ........................................................................................................14
Figure 12. Codec Transmits Data Over Multiple SDIs.............................................................................15
Figure 13. Link Reset Timing...................................................................................................................19
Figure 14. Codec Initialization Sequence.................................................................................................20
Figure 15. Link Reset and Initialization Timing.......................................................................................79
Figure 16. Link Signals Timing ................................................................................................................80
Figure 17. Output and Input Timing .........................................................................................................81
Figure 18. Filter Connection.....................................................................................................................83
Figure 19. Front Panel Header Connection ..............................................................................................84
Figure 20. Jack Connection on Rear Panel...............................................................................................85
Figure 21. S/PDIF Input/Output Connection............................................................................................85
Figure 22. GPI Volume Control Implementation......................................................................................86
Figure 23. Volume Control by External Variable Resistor .......................................................................87
Figure 24. Digital Microphone Implementation-1....................................................................................88
Figure 25. Digital Microphone Implementation-2....................................................................................88
7.1+2 Channel High-Performance HDA Codec
With Content Protection
Block Diagram ..........................................................................................................................4
Analog Input/Output Unit .........................................................................................................5
Pin Assignments ........................................................................................................................6
HDA Link Protocol ...................................................................................................................9
Bit Timing ...............................................................................................................................10
Signaling Topology .................................................................................................................11
SDO Outbound Frame.............................................................................................................12
SDO Stream Tag is Indicated in SYNC ..................................................................................12
Striped Stream on Multiple SDOs...........................................................................................13
List of Figures
viii
ALC885 Series
Datasheet
Rev. 1.1