zl10036 Zarlink Semiconductor, zl10036 Datasheet - Page 20

• Manufacturer Part Number: zl10036
• Description: Digital Satellite Tuner With Rf Bypass
• Manufacturer: Zarlink Semiconductor

3.2
Two internal logic levels, MA1 and MA0, can be set to one of four possible logic states by the voltage applied to the
ADD pin (#16). These four states in turn define four different read and write addresses on the I²C bus, so that as
many as four separate devices can be individually addressed on one bus. This is of particular use in a multi-tuner
environment as required by PVR applications.
3.3
The ZL10036 status can be read by addressing the device in its slave transmitter mode by setting the LSB of the
address byte (the R/W bit) to a one. After the master transmits the correct address byte, the ZL10036 will
acknowledge its address, and transmit data in response to further clocks on the SCL input. If the master responds
with an acknowledge and further clocks, the status byte will be retransmitted until such time as the master fails to
send an acknowledge, when the ZL10036 will release the data bus, allowing the master to generate a stop
condition.
The individual bits in the status register have the following meanings:
3.3.1
This bit is set to a logic ‘1’ if the VccDIG supply to the PLL section has dropped below typically 3.6 V, e.g., when the
device is initially turned on. The bit is reset to ‘0’ when the read sequence is terminated by a STOP command.
When the POR bit is high, this indicates that the programmed information may have been corrupted and the device
reset to power up condition.
3.3.2
Bit 6 (FL) indicates whether the synthesizer is phase locked, a logic ‘1’ is present if the device is locked, and a logic
‘0’ if the device is unlocked.
Device Address Selection
Read Register
Power-On Reset Indicator (POR bit)
Frequency & Phase Lock (FL bit)
Vee (0 V or Gnd)
Open circuit
0.5 * DIGDEC (±20%)
DIGDEC
1. can be programmed with a single 30 k Ω resistor to DIGDEC
Address
ADD Pin Voltage
Bit No.
Status
Table 4 - Read Data Bit Format (MSB is Transmitted First)
(MSB)
POR
7
1
1
FL
6
1
Table 3 - Address Selection
MA1
Zarlink Semiconductor Inc.
0
0
1
1
X
5
0
ZL10036
MA0
0
1
0
1
20
X
4
0
Write Address
0xC0
0xC2
0xC4
0xC6
Hex.
X
3
0
Dec.
192
194
196
198
MA1
X
2
MA0
Read Address
0xC1
0xC3
0xC5
0xC7
Hex.
X
1
(LSB)
X
0
1
Dec.
193
195
197
199
Data Sheet