zl10036 Zarlink Semiconductor, zl10036 Datasheet - Page 21

• Manufacturer Part Number: zl10036
• Description: Digital Satellite Tuner With Rf Bypass
• Manufacturer: Zarlink Semiconductor

3.3.3
These bits indicate internal logic states and are not required for normal use of the ZL10036.
3.4
The ZL10036 has twelve registers which can be programmed by addressing the device in its slave receiver mode,
setting the LSB of the address byte (the R/W bit) to a zero. After the master transmits the correct address byte, the
ZL10036 will acknowledge its address, and accept data in response to further clocks on the SCL line. At the end of
each byte, the ZL10036 will generate the acknowledge bit. The master can at this point, generate a stop condition,
or further clocks on the SCL line if further registers are to be programmed. If data is written after the twelfth register
(byte-13), it will be ignored.
3.4.1
If some register bits require changing, but not all, it is not necessary to write to all the registers. The registers can be
addressed in pairs starting with the even numbered bytes, i.e., 2 & 3, 4 & 5, etc. Table 5 below shows the protocol
required to address any of the even numbered register bytes. It therefore follows that to write to register byte-7 for
instance, byte-6 must also be written first. Register pairs may be written in any order, as required by the software,
e.g., 10/11 may be followed by 4/5.
Write Registers
Internal Operation Indicators (X Bits)
Register Sub-Addressing
Table 5 - Byte Address Allocation in Write Mode
‘X’ = Don’t care (content defines a register bit).
(MSB)
7
0
1
1
1
1
1
Data Bits
X
6
0
1
1
1
1
Zarlink Semiconductor Inc.
ZL10036
X
X
5
0
0
1
1
21
X
X
4
0
1
0
1
Byte Selected
10
12
2
4
6
8
Data Sheet