zl10036 Zarlink Semiconductor, zl10036 Datasheet - Page 25

• Manufacturer Part Number: zl10036
• Description: Digital Satellite Tuner With Rf Bypass
• Manufacturer: Zarlink Semiconductor

3.4.12
Register bits R4:0 control the reference divider ratios as shown in Table 13. They are programmed through bit-4 to
bit-0 respectively, in byte-5.
3.4.13
The baseband filters use a resistor switching technique that improves bandwidth and phase matching between the
I and Q channels. The bandwidth range is effectively separated into 3 sub-ranges with different resistor values
being used in each sub-range. It is possible for the filter bandwidth accuracy to be degraded if the bandwidth setting
happens to coincide with one of the two transition points between these regions. This can be overcome by disabling
the resistor switching using the RSD bit. For optimum filter performance the RSD bit should first be enabled so that
the correct resistor value is automatically set for the selected bandwidth.
The RSD bit (bit-3 of byte-6) controls the resistor switching. With the default setting of logic '0' it is enabled and the
correct resistor value automatically chosen. With the RSD bit set to a logic '1' then the switching is disabled and this
freezes the resistors at their chosen value. The procedure when selecting a new bandwidth setting is to enable then
disable the switching; set RSD to logic '0' then to logic '1'.
3.4.14
Bits 6 to 1 of byte-7 configure bits BF6 to BF1 respectively. These bits set a decimal number in the range 0 to 62
(63 is not allowed) to determine the baseband filter bandwidth in conjunction with other values.
Bits 6 to 2 of byte-13 configure bits BR4 to BR0 respectively. These bits set the reference divider ratio for the
baseband filter. A number in the range 4 to 27 inclusive (values outside this range are not allowed) can be set, with
the proviso that the value of f
For further details, please also see 2.4, “Baseband Filter“ on page 17 and “Symbol Rate and Filter Calculations”
(sect. 4.3) on page 26.
3.4.15
For test purposes, the LO clock divided by the prescaler ratio can be output on the LOTEST pin by setting bit TL
(byte-13 bit-0) to a logic ‘1’. By default this output is off, i.e., the TL bit is at logic ‘0’.
Reference Division Ratios (R4:0 Bits)
Baseband Filter Resistor Switching (RSD)
Baseband Filter Bandwidth (BF6:1 & BR4:0 Bits)
LO Test (TL Bit)
xtal
Table 13 - Division Ratios Set with Bits R4 - R0
/BR4:0 must also be in the range 575 kHz to 2,500 kHz.
R2
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
R4
R3
R0
0
1
0
1
0
1
0
1
Zarlink Semiconductor Inc.
128
256
ZL10036
0
0
16
32
64
2
4
8
25
Division Ratios
160
320
10
20
40
80
0
1
5
Illegal states
192
384
12
24
48
96
1
0
6
224
448
112
14
28
56
1
1
7
Data Sheet