ml2722 Sirenza Microdevices, ml2722 Datasheet - Page 22

• Manufacturer Part Number: ml2722
• Description: 900mhz Low-if 1.5mbps Fsk Transceiver
• Manufacturer: Sirenza Microdevices

CONTROL REGISTER DESCRIPTIONS
Power-On State
All register values are set to 0 (zero) on Power Up. Power up is defined as occurring when VDD (pin 31) ≥ 2.0V
(typical). The register default values are valid after power up. The PLL divide ratio and PLL configuration registers must
be programmed before XCEN is asserted for the first time.
Address and Data Bits (ADR)
Each of the three registers are identically configured. Each is divided into a fourteen (14) bit data field and a two (2) bit
address field. The 16 bits are input serially (see Figure 5) with the 14 data bits, most significant bit (DB13) first followed
by the two address bits, most significant bit (ADR1) first. The last 16 bits clocked into the ML2722 will be loaded into the
specified register. Loading less than 16 bits into any register will cause unpredictable device functionality.
RES Bit Locations (Reserved)
Bits identified as reserved must always have a logic 0 (zero) value for correct device operation. Power-on reset clears
all reserved bits to zero. Each reserved bit must be programmed to logic zero whenever any of the three registers are
reprogrammed.
DS2722-F-06
B15 (MSB) / DB13
B0 (LSB) / ADB0
B14 / DB12
B13 / DB11
B12 / DB10
DATA BIT
B11 / DB9
B10 / DB8
B1 / ADB1
B9 / DB7
B8 / DB6
B7 / DB5
B6 / DB4
B5 / DB3
B4 / DB2
B3 / DB1
B2 / DB0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NAME
ATM 1
ATM 0
DTM2
DTM1
DTM0
ATM2
ADR1
ADR0
Analog Test Control Bits
Digital Test Control Bits
Table 6. Register 2 – Test Mode Register
MSB Address Bit
LSB Address Bit
DESCRIPTION
Reserved
FINAL DATASHEET
ADR1 = 1
ADR0 = 0
Set all bits to 0 (zero)
See Table 15
See Table 14
USE
DECEMBER 2005
ML2722
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